From: Christoph Hellwig <hch@lst.de>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com>,
Dan Williams <dan.j.williams@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
dave.jiang@intel.com, alison.schofield@intel.com,
bwidawsk@kernel.org, vishal.l.verma@intel.com,
a.manzanares@samsung.com, linux-cxl@vger.kernel.org,
linux-kernel@vger.kernel.org, Bjorn Helgaas <bhelgaas@google.com>,
linux-pci@vger.kernel.org, Christoph Hellwig <hch@lst.de>
Subject: Re: [PATCH 1/2] cxl/pci: Add generic MSI-X/MSI irq support
Date: Sun, 30 Oct 2022 09:38:38 +0100 [thread overview]
Message-ID: <20221030083838.GD4949@lst.de> (raw)
In-Reply-To: <20221025232535.GA579167@bhelgaas>
On Tue, Oct 25, 2022 at 06:25:35PM -0500, Bjorn Helgaas wrote:
> Is this cxl code allocating vectors for devices that might also be
> claimed by portdrv? I assume not because that sounds like a problem.
>
> Ugh. I always feel like the portdrv design must be sub-optimal
> because this seems so hard to do cleanly.
Yes, portdrv is a mess. And I fear we really need to bite the bullet
rather sooner than later to sort much of this out by lifting all the
logic to the core and just keep the "drivers" around for sysfs
pretence.
And I think CXL is trying to run into a similar (but not quiete as bad)
mess with it's overly modular approach. In either case the right
thing would be to do anough early setup to find the requird number of
interrupts and highest interrupt number and just request that once.
next prev parent reply other threads:[~2022-10-30 8:38 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-18 3:00 [PATCH v3 0/2] cxl: Add general MSI-X/MSI irq support Davidlohr Bueso
2022-10-18 3:00 ` [PATCH 1/2] cxl/pci: Add generic " Davidlohr Bueso
2022-10-18 9:36 ` Jonathan Cameron
2022-10-18 10:52 ` Jonathan Cameron
2022-10-20 22:31 ` Davidlohr Bueso
2022-10-21 4:18 ` Ira Weiny
2022-10-21 8:49 ` Jonathan Cameron
2022-10-21 16:20 ` Davidlohr Bueso
2022-10-21 21:05 ` Ira Weiny
2022-10-21 4:14 ` Ira Weiny
2022-10-21 8:58 ` Jonathan Cameron
2022-10-21 15:58 ` Davidlohr Bueso
2022-10-22 22:17 ` Dan Williams
2022-10-18 11:17 ` Jonathan Cameron
2022-10-22 22:05 ` Dan Williams
2022-10-24 0:09 ` Ira Weiny
2022-10-24 2:08 ` Dan Williams
2022-10-24 12:36 ` Jonathan Cameron
2022-10-25 23:25 ` Bjorn Helgaas
2022-10-30 8:38 ` Christoph Hellwig [this message]
2022-11-02 17:15 ` Davidlohr Bueso
2022-11-02 22:54 ` Bjorn Helgaas
2022-11-02 23:42 ` Ira Weiny
2022-11-03 0:18 ` Davidlohr Bueso
2022-11-03 18:09 ` Jonathan Cameron
2022-11-10 3:30 ` Ira Weiny
2022-11-11 21:18 ` Davidlohr Bueso
2022-11-03 18:08 ` Jonathan Cameron
2022-10-18 3:00 ` [PATCH 2/2] cxl/mbox: Wire up " Davidlohr Bueso
2022-10-18 9:38 ` Jonathan Cameron
2022-10-21 17:23 ` Davidlohr Bueso
2022-10-22 22:14 ` Dan Williams
2022-10-22 22:06 ` Dan Williams
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