From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756933AbcAMK0f (ORCPT ); Wed, 13 Jan 2016 05:26:35 -0500 Received: from mo4-p00-ob.smtp.rzone.de ([81.169.146.219]:63307 "EHLO mo4-p00-ob.smtp.rzone.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756832AbcAMKZ6 convert rfc822-to-8bit (ORCPT ); Wed, 13 Jan 2016 05:25:58 -0500 X-RZG-AUTH: :JGIXVUS7cutRB/49FwqZ7WcKdUCnXG6JabOfSXKWrat6m8zoyY0= X-RZG-CLASS-ID: mo00 Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 7.3 \(1878.6\)) Subject: Re: [PATCH 1/3] ARM: dts: omap5-board-common: enable rtc and charging of backup battery From: "H. Nikolaus Schaller" In-Reply-To: Date: Wed, 13 Jan 2016 11:25:38 +0100 Cc: Laxman Dewangan , Nishanth Menon , =?iso-8859-1?Q?Beno=EEt_Cousson?= , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Russell King , linux-omap , devicetree@vger.kernel.org, LKML , Marek Belisko , =?windows-1252?Q?Gra=9Evydas_Ignotas?= Content-Transfer-Encoding: 8BIT Message-Id: <001346CD-CF31-4FEF-B406-B89EEBDFA063@goldelico.com> References: <8FE6954B-6411-4593-9CE5-717A469A6AA8@goldelico.com> <20160106164136.GI12777@atomide.com> <2AC46952-3758-458A-B0A5-1794C207BD4C@goldelico.com> <20160106170925.GK12777@atomide.com> <66F37918-EA7F-4D83-8B5F-A6B5C0CD7623@goldelico.com> <20160108181551.GX12777@atomide.com> <832803EE-E4CB-46B1-BF39-2DC0BB695A5D@goldelico.com> <20160108190457.GY12777@atomide.com> <20160111202421.GA12777@atomide.com> <20160112000917.GC12777@atomide.com> <417BBA32-A7DC-40CD-8A6B-EA910B1C9C13@goldelico.com> To: Tony Lindgren X-Mailer: Apple Mail (2.1878.6) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Tony, Am 12.01.2016 um 22:27 schrieb H. Nikolaus Schaller : > Hi Tony, > > Am 12.01.2016 um 14:30 schrieb H. Nikolaus Schaller : > >> Hi Tony, >> >> Am 12.01.2016 um 01:09 schrieb Tony Lindgren : >> >>> * Tony Lindgren [160111 12:27]: >>>> >>>> OK so the issue is that the twl msecure pin should be high to enable >>>> the RTC registers. We used to have that code with platform_data, but >>>> no longer have it with device tree based booting. I'll send a patch >>>> for that. >>>> >>>> Curiously setting jumper j5 on beagle-x15 that controls what used to >>>> be the msecure and now is powerhold, does the opposite.. The >>>> device boots automatically but RTC is stopped? >>> >>> And here's a fix the issue for omap5. Beagle-x15 needs to be >>> investigated more. >>> >>> Care to test it with your RTC enabling patch? >> >> yes, I will test asap. >> >> Reminds me on some issues we did have with msecure and twl4030 rtc some years ago. > > Ok, works for me on OMAP5432EVM. Yes, it works, but I didn't look into the code yet. > > Thanks for spotting the issue. > >> >> BR, >> Nikolaus >> >>> >>> Regards, >>> >>> Tony >>> >>> 8< --------------- >>> From: Tony Lindgren >>> Date: Mon, 11 Jan 2016 14:35:24 -0800 >>> Subject: [PATCH] ARM: dts: Fix omap5 PMIC control lines for RTC writes >>> >>> The palmas PMIC has some control lines that need to be muxed properly >>> for things to work. The sys_nirq pin is used for interrupts, and msecure >>> pin is used for enabling writes to some PMIC registers. >>> >>> Without these pins configured properly things can fail in mysterious >>> ways. For example, we can't update the RTC registers on palmas PMIC >>> unless the msecure pin is configured. And this is probably the reason >>> why we had RTC missing from the omap5 dts file. >>> >>> According to "OMAP5430 ES2.0 Data Manual [Public] VErsion A (Rev. F)" >>> swps052f.pdf, mux mode 1 is for sys_drm_msecure so there's no need to >>> configure it as a GPIO pin. >>> >>> Signed-off-by: Tony Lindgren >>> >>> --- a/arch/arm/boot/dts/omap5-board-common.dtsi >>> +++ b/arch/arm/boot/dts/omap5-board-common.dtsi >>> @@ -213,6 +213,12 @@ >>> >; >>> }; >>> >>> + palmas_msecure_pins: palmas_msecure_pins { >>> + pinctrl-single,pins = < >>> + OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE1) /* gpio8_234.sys_drm_msecure */ I wonder now what MODE1 is. In my OMAP5 TRM (Version "Y" - may be too old) the MODE1 is tagged as "reserved". Maybe "reserved" happens to output a "1" on OMAP5 and a "0" on the X15? And as far as I am aware there is no "driver" for some MSECURE module (but I don't know the details of MSECURE control by software). This one >>> OMAP5_IOPAD(0x180, PIN_INPUT _PULLUP | MUX_MODE6) /* gpio8_234 used for sys_drm_msecure */ works for me on the OMAP5 EVM as well. BR, Nikolaus >>> + >; >>> + }; >>> + >>> usbhost_pins: pinmux_usbhost_pins { >>> pinctrl-single,pins = < >>> 0x84 (PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */ >>> @@ -278,6 +284,12 @@ >>> &usbhost_wkup_pins >>> >; >>> >>> + palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins { >>> + pinctrl-single,pins = < >>> + OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1 */ >>> + >; >>> + }; >>> + >>> usbhost_wkup_pins: pinmux_usbhost_wkup_pins { >>> pinctrl-single,pins = < >>> 0x1A (PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */ >>> @@ -345,6 +357,8 @@ >>> interrupt-controller; >>> #interrupt-cells = <2>; >>> ti,system-power-controller; >>> + pinctrl-names = "default"; >>> + pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>; >>> >>> extcon_usb3: palmas_usb { >>> compatible = "ti,palmas-usb-vid"; >> >