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Tue, 06 Jul 2021 18:09:44 -0700 (PDT) Subject: Re: [RFC PATCH 8/8] target/i386: Move X86XSaveArea into TCG To: David Edmondson , qemu-devel@nongnu.org Cc: Michael Roth , kvm@vger.kernel.org, Roman Bolshakov , Paolo Bonzini , Marcelo Tosatti , babu.moger@amd.com, Cameron Esfahani , Eduardo Habkost References: <20210705104632.2902400-1-david.edmondson@oracle.com> <20210705104632.2902400-9-david.edmondson@oracle.com> From: Richard Henderson Message-ID: <0d75c3ab-926b-d4cd-244a-8c8b603535f9@linaro.org> Date: Tue, 6 Jul 2021 18:09:42 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210705104632.2902400-9-david.edmondson@oracle.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On 7/5/21 3:46 AM, David Edmondson wrote: > Given that TCG is now the only consumer of X86XSaveArea, move the > structure definition and associated offset declarations and checks to a > TCG specific header. > > Signed-off-by: David Edmondson > --- > target/i386/cpu.h | 57 ------------------------------------ > target/i386/tcg/fpu_helper.c | 1 + > target/i386/tcg/tcg-cpu.h | 57 ++++++++++++++++++++++++++++++++++++ > 3 files changed, 58 insertions(+), 57 deletions(-) > > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index 96b672f8bd..0f7ddbfeae 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -1305,48 +1305,6 @@ typedef struct XSavePKRU { > uint32_t padding; > } XSavePKRU; > > -#define XSAVE_FCW_FSW_OFFSET 0x000 > -#define XSAVE_FTW_FOP_OFFSET 0x004 > -#define XSAVE_CWD_RIP_OFFSET 0x008 > -#define XSAVE_CWD_RDP_OFFSET 0x010 > -#define XSAVE_MXCSR_OFFSET 0x018 > -#define XSAVE_ST_SPACE_OFFSET 0x020 > -#define XSAVE_XMM_SPACE_OFFSET 0x0a0 > -#define XSAVE_XSTATE_BV_OFFSET 0x200 > -#define XSAVE_AVX_OFFSET 0x240 > -#define XSAVE_BNDREG_OFFSET 0x3c0 > -#define XSAVE_BNDCSR_OFFSET 0x400 > -#define XSAVE_OPMASK_OFFSET 0x440 > -#define XSAVE_ZMM_HI256_OFFSET 0x480 > -#define XSAVE_HI16_ZMM_OFFSET 0x680 > -#define XSAVE_PKRU_OFFSET 0xa80 > - > -typedef struct X86XSaveArea { > - X86LegacyXSaveArea legacy; > - X86XSaveHeader header; > - > - /* Extended save areas: */ > - > - /* AVX State: */ > - XSaveAVX avx_state; > - > - /* Ensure that XSaveBNDREG is properly aligned. */ > - uint8_t padding[XSAVE_BNDREG_OFFSET > - - sizeof(X86LegacyXSaveArea) > - - sizeof(X86XSaveHeader) > - - sizeof(XSaveAVX)]; > - > - /* MPX State: */ > - XSaveBNDREG bndreg_state; > - XSaveBNDCSR bndcsr_state; > - /* AVX-512 State: */ > - XSaveOpmask opmask_state; > - XSaveZMM_Hi256 zmm_hi256_state; > - XSaveHi16_ZMM hi16_zmm_state; > - /* PKRU State: */ > - XSavePKRU pkru_state; > -} X86XSaveArea; > - > QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); > QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); > QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); > @@ -1355,21 +1313,6 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); > QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); > QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); > > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fcw) != XSAVE_FCW_FSW_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.ftw) != XSAVE_FTW_FOP_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpip) != XSAVE_CWD_RIP_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpdp) != XSAVE_CWD_RDP_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.mxcsr) != XSAVE_MXCSR_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpregs) != XSAVE_ST_SPACE_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.xmm_regs) != XSAVE_XMM_SPACE_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != XSAVE_AVX_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != XSAVE_BNDREG_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != XSAVE_BNDCSR_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != XSAVE_OPMASK_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != XSAVE_ZMM_HI256_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != XSAVE_HI16_ZMM_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != XSAVE_PKRU_OFFSET); > - > typedef struct ExtSaveArea { > uint32_t feature, bits; > uint32_t offset, size; > diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c > index 4e11965067..74bbe94b80 100644 > --- a/target/i386/tcg/fpu_helper.c > +++ b/target/i386/tcg/fpu_helper.c > @@ -20,6 +20,7 @@ > #include "qemu/osdep.h" > #include > #include "cpu.h" > +#include "tcg-cpu.h" > #include "exec/helper-proto.h" > #include "fpu/softfloat.h" > #include "fpu/softfloat-macros.h" > diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h > index 36bd300af0..53a8494455 100644 > --- a/target/i386/tcg/tcg-cpu.h > +++ b/target/i386/tcg/tcg-cpu.h > @@ -19,6 +19,63 @@ > #ifndef TCG_CPU_H > #define TCG_CPU_H > > +#define XSAVE_FCW_FSW_OFFSET 0x000 > +#define XSAVE_FTW_FOP_OFFSET 0x004 > +#define XSAVE_CWD_RIP_OFFSET 0x008 > +#define XSAVE_CWD_RDP_OFFSET 0x010 > +#define XSAVE_MXCSR_OFFSET 0x018 > +#define XSAVE_ST_SPACE_OFFSET 0x020 > +#define XSAVE_XMM_SPACE_OFFSET 0x0a0 > +#define XSAVE_XSTATE_BV_OFFSET 0x200 > +#define XSAVE_AVX_OFFSET 0x240 > +#define XSAVE_BNDREG_OFFSET 0x3c0 > +#define XSAVE_BNDCSR_OFFSET 0x400 > +#define XSAVE_OPMASK_OFFSET 0x440 > +#define XSAVE_ZMM_HI256_OFFSET 0x480 > +#define XSAVE_HI16_ZMM_OFFSET 0x680 > +#define XSAVE_PKRU_OFFSET 0xa80 > + > +typedef struct X86XSaveArea { > + X86LegacyXSaveArea legacy; > + X86XSaveHeader header; > + > + /* Extended save areas: */ > + > + /* AVX State: */ > + XSaveAVX avx_state; > + > + /* Ensure that XSaveBNDREG is properly aligned. */ > + uint8_t padding[XSAVE_BNDREG_OFFSET > + - sizeof(X86LegacyXSaveArea) > + - sizeof(X86XSaveHeader) > + - sizeof(XSaveAVX)]; > + > + /* MPX State: */ > + XSaveBNDREG bndreg_state; > + XSaveBNDCSR bndcsr_state; > + /* AVX-512 State: */ > + XSaveOpmask opmask_state; > + XSaveZMM_Hi256 zmm_hi256_state; > + XSaveHi16_ZMM hi16_zmm_state; > + /* PKRU State: */ > + XSavePKRU pkru_state; > +} X86XSaveArea; > + > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fcw) != XSAVE_FCW_FSW_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.ftw) != XSAVE_FTW_FOP_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpip) != XSAVE_CWD_RIP_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpdp) != XSAVE_CWD_RDP_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.mxcsr) != XSAVE_MXCSR_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpregs) != XSAVE_ST_SPACE_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.xmm_regs) != XSAVE_XMM_SPACE_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != XSAVE_AVX_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != XSAVE_BNDREG_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != XSAVE_BNDCSR_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != XSAVE_OPMASK_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != XSAVE_ZMM_HI256_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != XSAVE_HI16_ZMM_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != XSAVE_PKRU_OFFSET); My only quibble is that these offsets are otherwise unused. This just becomes validation of compiler layout. I presume that XSAVE_BNDREG_OFFSET is not merely ROUND_UP(offsetof(avx_state) + sizeof(avx_state), some_pow2)? Do these offsets need to be migrated? Otherwise, how can one start a vm with kvm and then migrate to tcg? I presume the offsets above are constant for a given cpu, and that whatever cpu provides different offsets is not supported by tcg? Given the lack of avx, that's trivial these days... r~ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.1 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00317C07E96 for ; Wed, 7 Jul 2021 01:10:49 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 84D4961CAA for ; Wed, 7 Jul 2021 01:10:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 84D4961CAA Authentication-Results: mail.kernel.org; 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Tue, 06 Jul 2021 18:09:44 -0700 (PDT) Received: from [192.168.1.11] ([71.212.149.176]) by smtp.gmail.com with ESMTPSA id e24sm17995692pfn.127.2021.07.06.18.09.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 06 Jul 2021 18:09:44 -0700 (PDT) Subject: Re: [RFC PATCH 8/8] target/i386: Move X86XSaveArea into TCG To: David Edmondson , qemu-devel@nongnu.org References: <20210705104632.2902400-1-david.edmondson@oracle.com> <20210705104632.2902400-9-david.edmondson@oracle.com> From: Richard Henderson Message-ID: <0d75c3ab-926b-d4cd-244a-8c8b603535f9@linaro.org> Date: Tue, 6 Jul 2021 18:09:42 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.11.0 MIME-Version: 1.0 In-Reply-To: <20210705104632.2902400-9-david.edmondson@oracle.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , kvm@vger.kernel.org, Michael Roth , Marcelo Tosatti , Cameron Esfahani , babu.moger@amd.com, Roman Bolshakov , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 7/5/21 3:46 AM, David Edmondson wrote: > Given that TCG is now the only consumer of X86XSaveArea, move the > structure definition and associated offset declarations and checks to a > TCG specific header. > > Signed-off-by: David Edmondson > --- > target/i386/cpu.h | 57 ------------------------------------ > target/i386/tcg/fpu_helper.c | 1 + > target/i386/tcg/tcg-cpu.h | 57 ++++++++++++++++++++++++++++++++++++ > 3 files changed, 58 insertions(+), 57 deletions(-) > > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index 96b672f8bd..0f7ddbfeae 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -1305,48 +1305,6 @@ typedef struct XSavePKRU { > uint32_t padding; > } XSavePKRU; > > -#define XSAVE_FCW_FSW_OFFSET 0x000 > -#define XSAVE_FTW_FOP_OFFSET 0x004 > -#define XSAVE_CWD_RIP_OFFSET 0x008 > -#define XSAVE_CWD_RDP_OFFSET 0x010 > -#define XSAVE_MXCSR_OFFSET 0x018 > -#define XSAVE_ST_SPACE_OFFSET 0x020 > -#define XSAVE_XMM_SPACE_OFFSET 0x0a0 > -#define XSAVE_XSTATE_BV_OFFSET 0x200 > -#define XSAVE_AVX_OFFSET 0x240 > -#define XSAVE_BNDREG_OFFSET 0x3c0 > -#define XSAVE_BNDCSR_OFFSET 0x400 > -#define XSAVE_OPMASK_OFFSET 0x440 > -#define XSAVE_ZMM_HI256_OFFSET 0x480 > -#define XSAVE_HI16_ZMM_OFFSET 0x680 > -#define XSAVE_PKRU_OFFSET 0xa80 > - > -typedef struct X86XSaveArea { > - X86LegacyXSaveArea legacy; > - X86XSaveHeader header; > - > - /* Extended save areas: */ > - > - /* AVX State: */ > - XSaveAVX avx_state; > - > - /* Ensure that XSaveBNDREG is properly aligned. */ > - uint8_t padding[XSAVE_BNDREG_OFFSET > - - sizeof(X86LegacyXSaveArea) > - - sizeof(X86XSaveHeader) > - - sizeof(XSaveAVX)]; > - > - /* MPX State: */ > - XSaveBNDREG bndreg_state; > - XSaveBNDCSR bndcsr_state; > - /* AVX-512 State: */ > - XSaveOpmask opmask_state; > - XSaveZMM_Hi256 zmm_hi256_state; > - XSaveHi16_ZMM hi16_zmm_state; > - /* PKRU State: */ > - XSavePKRU pkru_state; > -} X86XSaveArea; > - > QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100); > QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40); > QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40); > @@ -1355,21 +1313,6 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200); > QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400); > QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8); > > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fcw) != XSAVE_FCW_FSW_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.ftw) != XSAVE_FTW_FOP_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpip) != XSAVE_CWD_RIP_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpdp) != XSAVE_CWD_RDP_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.mxcsr) != XSAVE_MXCSR_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpregs) != XSAVE_ST_SPACE_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.xmm_regs) != XSAVE_XMM_SPACE_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != XSAVE_AVX_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != XSAVE_BNDREG_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != XSAVE_BNDCSR_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != XSAVE_OPMASK_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != XSAVE_ZMM_HI256_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != XSAVE_HI16_ZMM_OFFSET); > -QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != XSAVE_PKRU_OFFSET); > - > typedef struct ExtSaveArea { > uint32_t feature, bits; > uint32_t offset, size; > diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c > index 4e11965067..74bbe94b80 100644 > --- a/target/i386/tcg/fpu_helper.c > +++ b/target/i386/tcg/fpu_helper.c > @@ -20,6 +20,7 @@ > #include "qemu/osdep.h" > #include > #include "cpu.h" > +#include "tcg-cpu.h" > #include "exec/helper-proto.h" > #include "fpu/softfloat.h" > #include "fpu/softfloat-macros.h" > diff --git a/target/i386/tcg/tcg-cpu.h b/target/i386/tcg/tcg-cpu.h > index 36bd300af0..53a8494455 100644 > --- a/target/i386/tcg/tcg-cpu.h > +++ b/target/i386/tcg/tcg-cpu.h > @@ -19,6 +19,63 @@ > #ifndef TCG_CPU_H > #define TCG_CPU_H > > +#define XSAVE_FCW_FSW_OFFSET 0x000 > +#define XSAVE_FTW_FOP_OFFSET 0x004 > +#define XSAVE_CWD_RIP_OFFSET 0x008 > +#define XSAVE_CWD_RDP_OFFSET 0x010 > +#define XSAVE_MXCSR_OFFSET 0x018 > +#define XSAVE_ST_SPACE_OFFSET 0x020 > +#define XSAVE_XMM_SPACE_OFFSET 0x0a0 > +#define XSAVE_XSTATE_BV_OFFSET 0x200 > +#define XSAVE_AVX_OFFSET 0x240 > +#define XSAVE_BNDREG_OFFSET 0x3c0 > +#define XSAVE_BNDCSR_OFFSET 0x400 > +#define XSAVE_OPMASK_OFFSET 0x440 > +#define XSAVE_ZMM_HI256_OFFSET 0x480 > +#define XSAVE_HI16_ZMM_OFFSET 0x680 > +#define XSAVE_PKRU_OFFSET 0xa80 > + > +typedef struct X86XSaveArea { > + X86LegacyXSaveArea legacy; > + X86XSaveHeader header; > + > + /* Extended save areas: */ > + > + /* AVX State: */ > + XSaveAVX avx_state; > + > + /* Ensure that XSaveBNDREG is properly aligned. */ > + uint8_t padding[XSAVE_BNDREG_OFFSET > + - sizeof(X86LegacyXSaveArea) > + - sizeof(X86XSaveHeader) > + - sizeof(XSaveAVX)]; > + > + /* MPX State: */ > + XSaveBNDREG bndreg_state; > + XSaveBNDCSR bndcsr_state; > + /* AVX-512 State: */ > + XSaveOpmask opmask_state; > + XSaveZMM_Hi256 zmm_hi256_state; > + XSaveHi16_ZMM hi16_zmm_state; > + /* PKRU State: */ > + XSavePKRU pkru_state; > +} X86XSaveArea; > + > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fcw) != XSAVE_FCW_FSW_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.ftw) != XSAVE_FTW_FOP_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpip) != XSAVE_CWD_RIP_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpdp) != XSAVE_CWD_RDP_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.mxcsr) != XSAVE_MXCSR_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.fpregs) != XSAVE_ST_SPACE_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, legacy.xmm_regs) != XSAVE_XMM_SPACE_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != XSAVE_AVX_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != XSAVE_BNDREG_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != XSAVE_BNDCSR_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != XSAVE_OPMASK_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != XSAVE_ZMM_HI256_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != XSAVE_HI16_ZMM_OFFSET); > +QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != XSAVE_PKRU_OFFSET); My only quibble is that these offsets are otherwise unused. This just becomes validation of compiler layout. I presume that XSAVE_BNDREG_OFFSET is not merely ROUND_UP(offsetof(avx_state) + sizeof(avx_state), some_pow2)? Do these offsets need to be migrated? Otherwise, how can one start a vm with kvm and then migrate to tcg? I presume the offsets above are constant for a given cpu, and that whatever cpu provides different offsets is not supported by tcg? Given the lack of avx, that's trivial these days... r~