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From: Hans Rosenfeld <hans.rosenfeld@amd.com>
To: <hpa@zytor.com>, <tglx@linutronix.de>, <mingo@elte.hu>
Cc: <linux-kernel@vger.kernel.org>, <andreas.herrmann3@amd.com>,
	Hans Rosenfeld <hans.rosenfeld@amd.com>
Subject: [PATCH 2/4] x86, amd: Enable L3 cache index disable on family 0x15
Date: Mon, 20 Dec 2010 18:13:45 +0100	[thread overview]
Message-ID: <1292865227-647466-3-git-send-email-hans.rosenfeld@amd.com> (raw)
In-Reply-To: <1292865227-647466-1-git-send-email-hans.rosenfeld@amd.com>

AMD family 0x15 CPUs support L3 cache index disable, so enable it on
them.

Signed-off-by: Hans Rosenfeld <hans.rosenfeld@amd.com>
---
 arch/x86/kernel/amd_nb.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index affacb5..4ce87c2 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -78,6 +78,9 @@ int amd_cache_northbridges(void)
 	     boot_cpu_data.x86_mask >= 0x1))
 		amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
 
+	if (boot_cpu_data.x86 == 0x15)
+		amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(amd_cache_northbridges);
-- 
1.5.6.5



  parent reply	other threads:[~2010-12-20 17:14 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-12-20 17:13 [PATCH 0/4] x86, amd: family 0x15 L3 cache features Hans Rosenfeld
2010-12-20 17:13 ` [PATCH 1/4] x86, amd: Normalize compute unit IDs on multi-node processors Hans Rosenfeld
2010-12-20 17:13 ` Hans Rosenfeld [this message]
2010-12-20 17:13 ` [PATCH 3/4] x86, amd: Extend AMD northbridge caching code to support "Link Control" devices Hans Rosenfeld
2010-12-20 17:13 ` [PATCH 4/4] x86, amd: Support L3 Cache Partitioning on AMD family 0x15 CPUs Hans Rosenfeld
2011-01-24 15:05 [PATCH 0/4] x86, amd: family 0x15 L3 cache features Hans Rosenfeld
2011-01-24 15:05 ` [PATCH 2/4] x86, amd: Enable L3 cache index disable on family 0x15 Hans Rosenfeld

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