Re: [PATCH 7/7] xen/arm: phys_timer fixes

[Ian Campbell <Ian.Campbell@citrix.com>]

On Mon, 2013-02-18 at 16:14 +0000, Stefano Stabellini wrote:
> I think they mean "latch" in electronic sense: they use an SR latch to
> keep the pending bit high even if the guest EOIs the interrupt, as long
> as the mask bit is 1.

> In other words the pending bit cannot be reset if the mask bit is 1.

"latching high" is a plausible interpretation of the docs given the
observed behaviour on the A15.

We shouldn't assume that just because it appears to behave on way on the
A15, for all we know the state of the PENDING bit while mask==0 is
explicitly implementation defined and just happens to follow the state
of the interrupt in this particular implementation (yes, this would make
Linux and Xen both buggy in their handling). After all we don't have any
alternative implementations to compare with...

So I'd still prefer to check with ARM, rather than potentially bake a
buggy "hardware" implementation into our interface.

> So I should prevent the guest from resetting this bit directly in all
> cases and also I should not reset the bit on EOI if the mask bit is 1.

You also need to do the right thing when the guest clears the mask bit,
which is going to require you to track if the interrupt has been EOId
separately from the pending bit.

> I agree that is confusing though.

Very!