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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: qemu-devel@nongnu.org, peter.maydell@linaro.org
Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com,
	aggelerf@ethz.ch, agraf@suse.de, blauwirbel@gmail.com,
	john.williams@xilinx.com, greg.bellows@linaro.org,
	pbonzini@redhat.com, alex.bennee@linaro.org,
	christoffer.dall@linaro.org, rth@twiddle.net
Subject: [Qemu-devel] [PATCH v2 06/17] target-arm: Add FAR_EL2 and 3
Date: Tue, 10 Jun 2014 01:04:18 +1000	[thread overview]
Message-ID: <1402326269-8573-7-git-send-email-edgar.iglesias@gmail.com> (raw)
In-Reply-To: <1402326269-8573-1-git-send-email-edgar.iglesias@gmail.com>

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target-arm/cpu.h    | 2 +-
 target-arm/helper.c | 6 ++++++
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 2ee3da2..5114d26 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -187,7 +187,7 @@ typedef struct CPUARMState {
         uint32_t ifsr_el2; /* Fault status registers.  */
         uint64_t esr_el[4];
         uint32_t c6_region[8]; /* MPU base/size registers.  */
-        uint64_t far_el[2]; /* Fault address registers.  */
+        uint64_t far_el[4]; /* Fault address registers.  */
         uint64_t par_el1;  /* Translation result. */
         uint32_t c9_insn; /* Cache lockdown registers.  */
         uint32_t c9_data;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6eb7815..90874c4 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2120,6 +2120,9 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
       .type = ARM_CP_NO_MIGRATE,
       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
+    { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
+      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
       .type = ARM_CP_NO_MIGRATE,
       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
@@ -2142,6 +2145,9 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
       .type = ARM_CP_NO_MIGRATE,
       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
+    { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
+      .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
       .type = ARM_CP_NO_MIGRATE,
       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
-- 
1.8.3.2

  parent reply	other threads:[~2014-06-09 15:09 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-09 15:04 [Qemu-devel] [PATCH v2 00/17] target-arm: Parts of the AArch64 EL2/3 exception model Edgar E. Iglesias
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 01/17] target-arm: A64: Break out aarch64_save/restore_sp Edgar E. Iglesias
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 02/17] target-arm: A64: Respect SPSEL in ERET SP restore Edgar E. Iglesias
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 03/17] target-arm: A64: Respect SPSEL when taking exceptions Edgar E. Iglesias
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 04/17] target-arm: Make far_el1 an array Edgar E. Iglesias
2014-06-11 15:11   ` Greg Bellows
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 05/17] target-arm: Add ESR_EL2 and 3 Edgar E. Iglesias
2014-06-11 15:13   ` Greg Bellows
2014-06-09 15:04 ` Edgar E. Iglesias [this message]
2014-06-11 15:15   ` [Qemu-devel] [PATCH v2 06/17] target-arm: Add FAR_EL2 " Greg Bellows
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 07/17] target-arm: Add HCR_EL2 Edgar E. Iglesias
2014-06-11 15:48   ` Greg Bellows
2014-06-11 15:58     ` Greg Bellows
2014-06-16  6:36     ` Edgar E. Iglesias
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 08/17] target-arm: Add SCR_EL3 Edgar E. Iglesias
2014-06-10 22:06   ` Aggeler  Fabian
2014-06-11  1:19     ` Edgar E. Iglesias
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 09/17] target-arm: A64: Refactor aarch64_cpu_do_interrupt Edgar E. Iglesias
2014-06-11 16:51   ` Greg Bellows
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 10/17] target-arm: Break out exception masking to a separate func Edgar E. Iglesias
2014-06-11 17:16   ` Greg Bellows
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 11/17] target-arm: Don't take interrupts targeting lower ELs Edgar E. Iglesias
2014-06-11 17:17   ` Greg Bellows
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 12/17] target-arm: A64: Correct updates to FAR and ESR on exceptions Edgar E. Iglesias
2014-06-11 18:36   ` Greg Bellows
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 13/17] target-arm: Use uint16_t in syndrome generators with 16bit imms Edgar E. Iglesias
2014-06-11 19:19   ` Greg Bellows
2014-06-11 21:05     ` Peter Maydell
2014-06-11 21:19       ` Greg Bellows
2014-06-16 23:13       ` Edgar E. Iglesias
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 14/17] target-arm: A64: Emulate the HVC insn Edgar E. Iglesias
2014-06-11 20:14   ` Greg Bellows
2014-06-16 23:28     ` Edgar E. Iglesias
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 15/17] target-arm: A64: Emulate the SMC insn Edgar E. Iglesias
2014-06-11 21:14   ` Greg Bellows
2014-06-16  6:03     ` Edgar E. Iglesias
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 16/17] target-arm: Add IRQ and FIQ routing to EL2 and 3 Edgar E. Iglesias
2014-06-11 22:08   ` Greg Bellows
2014-06-09 15:04 ` [Qemu-devel] [PATCH v2 17/17] target-arm: Add support for VIRQ and VFIQ Edgar E. Iglesias
2014-06-11 22:31   ` Greg Bellows

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