diff for duplicates of <1428916660-25910-7-git-send-email-bintian.wang@huawei.com>
diff --git a/a/content_digest b/N1/content_digest
index 0cc0d8a..3b36926 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -11,49 +11,49 @@
"Date\0Mon, 13 Apr 2015 17:17:40 +0800\0"
]
[
- "To\0<linux-arm-kernel\@lists.infradead.org>",
- " <linux-kernel\@vger.kernel.org>",
- " <catalin.marinas\@arm.com>",
- " <will.deacon\@arm.com>",
- " <devicetree\@vger.kernel.org>",
- " <robh+dt\@kernel.org>",
- " <pawel.moll\@arm.com>",
- " <mark.rutland\@arm.com>",
- " <ijc+devicetree\@hellion.org.uk>",
- " <galak\@codeaurora.org>",
- " <khilman\@linaro.org>",
- " <mturquette\@linaro.org>",
- " <rob.herring\@linaro.org>",
- " <zhangfei.gao\@linaro.org>",
- " <haojian.zhuang\@linaro.org>",
- " <xuwei5\@hisilicon.com>",
- " <jh80.chung\@samsung.com>",
- " <olof\@lixom.net>",
- " <yanhaifeng\@gmail.com>",
- " <sboyd\@codeaurora.org>",
- " <xuejiancheng\@huawei.com>",
- " <sledge.yanwei\@huawei.com>",
- " <tomeu.vizoso\@collabora.com>",
- " <linux\@arm.linux.org.uk>",
- " <guodong.xu\@linaro.org>",
- " <jorge.ramirez-ortiz\@linaro.org>",
- " <tyler.baker\@linaro.org>\0"
+ "To\0linux-arm-kernel\@lists.infradead.org",
+ " linux-kernel\@vger.kernel.org",
+ " catalin.marinas\@arm.com",
+ " will.deacon\@arm.com",
+ " devicetree\@vger.kernel.org",
+ " robh+dt\@kernel.org",
+ " pawel.moll\@arm.com",
+ " mark.rutland\@arm.com",
+ " ijc+devicetree\@hellion.org.uk",
+ " galak\@codeaurora.org",
+ " khilman\@linaro.org",
+ " mturquette\@linaro.org",
+ " rob.herring\@linaro.org",
+ " zhangfei.gao\@linaro.org",
+ " haojian.zhuang\@linaro.org",
+ " xuwei5\@hisilicon.com",
+ " jh80.chung\@samsung.com",
+ " olof\@lixom.net",
+ " yanhaifeng\@gmail.com",
+ " sboyd\@codeaurora.org",
+ " xuejiancheng\@huawei.com",
+ " sledge.yanwei\@huawei.com",
+ " tomeu.vizoso\@collabora.com",
+ " linux\@arm.linux.org.uk",
+ " guodong.xu\@linaro.org",
+ " jorge.ramirez-ortiz\@linaro.org",
+ " tyler.baker\@linaro.org\0"
]
[
- "Cc\0<xuyiping\@hisilicon.com>",
- " <wangbinghui\@hisilicon.com>",
- " <zhenwei.wang\@hisilicon.com>",
- " <victor.lixin\@hisilicon.com>",
- " <puck.chen\@hisilicon.com>",
- " <dan.zhao\@hisilicon.com>",
- " <huxinwei\@huawei.com>",
- " <bintian.wang\@huawei.com>",
- " <z.liuxinliang\@huawei.com>",
- " <heyunlei\@huawei.com>",
- " <kong.kongxinwei\@hisilicon.com>",
- " <btw\@mail.itp.ac.cn>",
- " <w.f\@huawei.com>",
- " <liguozhu\@hisilicon.com>\0"
+ "Cc\0xuyiping\@hisilicon.com",
+ " wangbinghui\@hisilicon.com",
+ " zhenwei.wang\@hisilicon.com",
+ " victor.lixin\@hisilicon.com",
+ " puck.chen\@hisilicon.com",
+ " dan.zhao\@hisilicon.com",
+ " huxinwei\@huawei.com",
+ " bintian.wang\@huawei.com",
+ " z.liuxinliang\@huawei.com",
+ " heyunlei\@huawei.com",
+ " kong.kongxinwei\@hisilicon.com",
+ " btw\@mail.itp.ac.cn",
+ " w.f\@huawei.com",
+ " liguozhu\@hisilicon.com\0"
]
[
"\0000:1\0"
@@ -319,4 +319,4 @@
"1.9.1"
]
-a2ed53571b76d36decc1603c5ec41cb65c82b202805c60d7e339a9a7e38b8487
+a6e229aa972f3588f4d93872fd565f3648be0aee2e95495c7721b6bd3ad087d0
diff --git a/a/1.txt b/N2/1.txt
index d68e3b6..d2fe5e1 100644
--- a/a/1.txt
+++ b/N2/1.txt
@@ -69,7 +69,7 @@ index 0000000..c4b3ed8
+ linux,stdout-path = &uart0;
+ };
+
-+ memory@0 {
++ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
@@ -134,56 +134,56 @@ index 0000000..ca0f64c
+ };
+ };
+
-+ cpu0: cpu@0 {
++ cpu0: cpu at 0 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
-+ cpu1: cpu@1 {
++ cpu1: cpu at 1 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
-+ cpu2: cpu@2 {
++ cpu2: cpu at 2 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+
-+ cpu3: cpu@3 {
++ cpu3: cpu at 3 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+
-+ cpu4: cpu@100 {
++ cpu4: cpu at 100 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ };
+
-+ cpu5: cpu@101 {
++ cpu5: cpu at 101 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ };
+
-+ cpu6: cpu@102 {
++ cpu6: cpu at 102 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
+ };
+
-+ cpu7: cpu@103 {
++ cpu7: cpu at 103 {
+ compatible = "arm,cortex-a53", "arm,armv8";
+ device_type = "cpu";
+ reg = <0x0 0x103>;
@@ -191,7 +191,7 @@ index 0000000..ca0f64c
+ };
+ };
+
-+ gic: interrupt-controller@f6801000 {
++ gic: interrupt-controller at f6801000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xf6801000 0 0x1000>, /* GICD */
+ <0x0 0xf6802000 0 0x2000>, /* GICC */
@@ -242,7 +242,7 @@ index 0000000..ca0f64c
+ #clock-cells = <1>;
+ };
+
-+ uart0: uart@f8015000 { /* console */
++ uart0: uart at f8015000 { /* console */
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x0 0xf8015000 0x0 0x1000>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/a/content_digest b/N2/content_digest
index 0cc0d8a..11c89a6 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -2,7 +2,7 @@
"ref\0001428916660-25910-1-git-send-email-bintian.wang\@huawei.com\0"
]
[
- "From\0Bintian Wang <bintian.wang\@huawei.com>\0"
+ "From\0bintian.wang\@huawei.com (Bintian Wang)\0"
]
[
"Subject\0[PATCH v2 6/6] arm64: dts: Add dts files for Hisilicon Hi6220 SoC\0"
@@ -11,49 +11,7 @@
"Date\0Mon, 13 Apr 2015 17:17:40 +0800\0"
]
[
- "To\0<linux-arm-kernel\@lists.infradead.org>",
- " <linux-kernel\@vger.kernel.org>",
- " <catalin.marinas\@arm.com>",
- " <will.deacon\@arm.com>",
- " <devicetree\@vger.kernel.org>",
- " <robh+dt\@kernel.org>",
- " <pawel.moll\@arm.com>",
- " <mark.rutland\@arm.com>",
- " <ijc+devicetree\@hellion.org.uk>",
- " <galak\@codeaurora.org>",
- " <khilman\@linaro.org>",
- " <mturquette\@linaro.org>",
- " <rob.herring\@linaro.org>",
- " <zhangfei.gao\@linaro.org>",
- " <haojian.zhuang\@linaro.org>",
- " <xuwei5\@hisilicon.com>",
- " <jh80.chung\@samsung.com>",
- " <olof\@lixom.net>",
- " <yanhaifeng\@gmail.com>",
- " <sboyd\@codeaurora.org>",
- " <xuejiancheng\@huawei.com>",
- " <sledge.yanwei\@huawei.com>",
- " <tomeu.vizoso\@collabora.com>",
- " <linux\@arm.linux.org.uk>",
- " <guodong.xu\@linaro.org>",
- " <jorge.ramirez-ortiz\@linaro.org>",
- " <tyler.baker\@linaro.org>\0"
-]
-[
- "Cc\0<xuyiping\@hisilicon.com>",
- " <wangbinghui\@hisilicon.com>",
- " <zhenwei.wang\@hisilicon.com>",
- " <victor.lixin\@hisilicon.com>",
- " <puck.chen\@hisilicon.com>",
- " <dan.zhao\@hisilicon.com>",
- " <huxinwei\@huawei.com>",
- " <bintian.wang\@huawei.com>",
- " <z.liuxinliang\@huawei.com>",
- " <heyunlei\@huawei.com>",
- " <kong.kongxinwei\@hisilicon.com>",
- " <btw\@mail.itp.ac.cn>",
- " <w.f\@huawei.com>",
- " <liguozhu\@hisilicon.com>\0"
+ "To\0linux-arm-kernel\@lists.infradead.org\0"
]
[
"\0000:1\0"
@@ -133,7 +91,7 @@
"+\t\tlinux,stdout-path = &uart0;\n",
"+\t};\n",
"+\n",
- "+\tmemory\@0 {\n",
+ "+\tmemory at 0 {\n",
"+\t\tdevice_type = \"memory\";\n",
"+\t\treg = <0x0 0x0 0x0 0x40000000>;\n",
"+\t};\n",
@@ -198,56 +156,56 @@
"+\t\t\t};\n",
"+\t\t};\n",
"+\n",
- "+\t\tcpu0: cpu\@0 {\n",
+ "+\t\tcpu0: cpu at 0 {\n",
"+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\treg = <0x0 0x0>;\n",
"+\t\t\tenable-method = \"psci\";\n",
"+\t\t};\n",
"+\n",
- "+\t\tcpu1: cpu\@1 {\n",
+ "+\t\tcpu1: cpu at 1 {\n",
"+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\treg = <0x0 0x1>;\n",
"+\t\t\tenable-method = \"psci\";\n",
"+\t\t};\n",
"+\n",
- "+\t\tcpu2: cpu\@2 {\n",
+ "+\t\tcpu2: cpu at 2 {\n",
"+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\treg = <0x0 0x2>;\n",
"+\t\t\tenable-method = \"psci\";\n",
"+\t\t};\n",
"+\n",
- "+\t\tcpu3: cpu\@3 {\n",
+ "+\t\tcpu3: cpu at 3 {\n",
"+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\treg = <0x0 0x3>;\n",
"+\t\t\tenable-method = \"psci\";\n",
"+\t\t};\n",
"+\n",
- "+\t\tcpu4: cpu\@100 {\n",
+ "+\t\tcpu4: cpu at 100 {\n",
"+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\treg = <0x0 0x100>;\n",
"+\t\t\tenable-method = \"psci\";\n",
"+\t\t};\n",
"+\n",
- "+\t\tcpu5: cpu\@101 {\n",
+ "+\t\tcpu5: cpu at 101 {\n",
"+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\treg = <0x0 0x101>;\n",
"+\t\t\tenable-method = \"psci\";\n",
"+\t\t};\n",
"+\n",
- "+\t\tcpu6: cpu\@102 {\n",
+ "+\t\tcpu6: cpu at 102 {\n",
"+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\treg = <0x0 0x102>;\n",
"+\t\t\tenable-method = \"psci\";\n",
"+\t\t};\n",
"+\n",
- "+\t\tcpu7: cpu\@103 {\n",
+ "+\t\tcpu7: cpu at 103 {\n",
"+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n",
"+\t\t\tdevice_type = \"cpu\";\n",
"+\t\t\treg = <0x0 0x103>;\n",
@@ -255,7 +213,7 @@
"+\t\t};\n",
"+\t};\n",
"+\n",
- "+\tgic: interrupt-controller\@f6801000 {\n",
+ "+\tgic: interrupt-controller at f6801000 {\n",
"+\t\tcompatible = \"arm,gic-400\";\n",
"+\t\treg = <0x0 0xf6801000 0 0x1000>, /* GICD */\n",
"+\t\t <0x0 0xf6802000 0 0x2000>, /* GICC */\n",
@@ -306,7 +264,7 @@
"+\t\t\t#clock-cells = <1>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tuart0: uart\@f8015000 {\t/* console */\n",
+ "+\t\tuart0: uart at f8015000 {\t/* console */\n",
"+\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n",
"+\t\t\treg = <0x0 0xf8015000 0x0 0x1000>;\n",
"+\t\t\tinterrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;\n",
@@ -319,4 +277,4 @@
"1.9.1"
]
-a2ed53571b76d36decc1603c5ec41cb65c82b202805c60d7e339a9a7e38b8487
+eadef5aaeb3a811eccc29e4e00f0777d3bfd910c3e16b3b24d8f2e3edf6570e3
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