From: Alex Porosanu <alexandru.porosanu@nxp.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/3] arch/arm, arch/powerpc: add # of SEC engines on the SOC
Date: Fri, 29 Apr 2016 15:17:59 +0300 [thread overview]
Message-ID: <1461932280-8723-3-git-send-email-alexandru.porosanu@nxp.com> (raw)
In-Reply-To: <1461932280-8723-1-git-send-email-alexandru.porosanu@nxp.com>
From: Alex Porosanu <alexandru.porosanu@freescale.com>
Some SOCs, specifically the ones in the C29x familiy can have
multiple security engines. This patch adds a system configuration
define which indicates the maximum number of SEC engines that
can be found on a SoC.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 2 ++
arch/arm/include/asm/arch-ls102xa/config.h | 1 +
arch/powerpc/include/asm/config_mpc85xx.h | 6 ++++++
board/freescale/c29xpcie/c29xpcie.c | 2 +-
4 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 10d17b2..5771b28 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -143,6 +143,7 @@
#define CONFIG_ARM_ERRATA_829520
#define CONFIG_ARM_ERRATA_833471
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#elif defined(CONFIG_LS1043A)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_CACHELINE_SIZE 64
@@ -195,6 +196,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A009929
#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_ERRATUM_A009660
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else
#error SoC not defined
#endif
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 92f30e2..139a623 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -132,6 +132,7 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_ERRATUM_A008378
#define CONFIG_SYS_FSL_ERRATUM_A009663
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else
#error SoC not defined
#endif
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index eccc146..505d355 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -928,6 +928,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_A005125
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 3
+#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
#elif defined(CONFIG_QEMU_E500)
#define CONFIG_MAX_CPUS 1
@@ -954,4 +956,8 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_SYS_FSL_DDRC_GEN3
#endif
+#if !defined(CONFIG_PPC_C29X)
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
+#endif
+
#endif /* _ASM_MPC85xx_CONFIG_H_ */
diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c
index e325b4d..45f463f 100644
--- a/board/freescale/c29xpcie/c29xpcie.c
+++ b/board/freescale/c29xpcie/c29xpcie.c
@@ -122,7 +122,7 @@ void fdt_del_sec(void *blob, int offset)
while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
- + offset * 0x20000)) >= 0) {
+ + offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
fdt_del_node(blob, nodeoff);
offset++;
}
--
1.9.3
next prev parent reply other threads:[~2016-04-29 12:17 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-04-29 12:17 [U-Boot] [PATCH 0/3] Multiple FSL Security Engine RNG instantation Alex Porosanu
2016-04-29 12:17 ` [U-Boot] [PATCH 1/3] arch/arm: add SEC JR0 offset Alex Porosanu
2016-04-29 12:17 ` Alex Porosanu [this message]
2016-04-29 12:18 ` [U-Boot] [PATCH 3/3] crypto/fsl: add support for multiple SEC engines initialization Alex Porosanu
2016-05-23 7:34 ` [U-Boot] [PATCH 0/3] Multiple FSL Security Engine RNG instantation Alexandru Porosanu
2016-05-24 17:18 ` York Sun
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