From: Rajendra Nayak <rnayak@codeaurora.org>
To: sboyd@codeaurora.org, mturquette@baylibre.com
Cc: linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, tdas@codeaurora.org,
Rajendra Nayak <rnayak@codeaurora.org>
Subject: [PATCH v2 08/10] clk: qcom: Cleanup some macro defs
Date: Thu, 11 Aug 2016 14:10:56 +0530 [thread overview]
Message-ID: <1470904858-11930-9-git-send-email-rnayak@codeaurora.org> (raw)
In-Reply-To: <1470904858-11930-1-git-send-email-rnayak@codeaurora.org>
From: Taniya Das <tdas@codeaurora.org>
Move all
'# define XYZ'
to
'#define XYZ'
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/clk-alpha-pll.c | 32 ++++++++++++++++----------------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index e8f3505..854487e 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -21,28 +21,28 @@
#include "common.h"
#define PLL_MODE 0x00
-# define PLL_OUTCTRL BIT(0)
-# define PLL_BYPASSNL BIT(1)
-# define PLL_RESET_N BIT(2)
-# define PLL_LOCK_COUNT_SHIFT 8
-# define PLL_LOCK_COUNT_MASK 0x3f
-# define PLL_BIAS_COUNT_SHIFT 14
-# define PLL_BIAS_COUNT_MASK 0x3f
-# define PLL_VOTE_FSM_ENA BIT(20)
-# define PLL_VOTE_FSM_RESET BIT(21)
-# define PLL_ACTIVE_FLAG BIT(30)
-# define PLL_LOCK_DET BIT(31)
+#define PLL_OUTCTRL BIT(0)
+#define PLL_BYPASSNL BIT(1)
+#define PLL_RESET_N BIT(2)
+#define PLL_LOCK_COUNT_SHIFT 8
+#define PLL_LOCK_COUNT_MASK 0x3f
+#define PLL_BIAS_COUNT_SHIFT 14
+#define PLL_BIAS_COUNT_MASK 0x3f
+#define PLL_VOTE_FSM_ENA BIT(20)
+#define PLL_VOTE_FSM_RESET BIT(21)
+#define PLL_ACTIVE_FLAG BIT(30)
+#define PLL_LOCK_DET BIT(31)
#define PLL_L_VAL 0x04
#define PLL_ALPHA_VAL 0x08
#define PLL_ALPHA_VAL_U 0x0c
#define PLL_USER_CTL 0x10
-# define PLL_POST_DIV_SHIFT 8
-# define PLL_POST_DIV_MASK 0xf
-# define PLL_ALPHA_EN BIT(24)
-# define PLL_VCO_SHIFT 20
-# define PLL_VCO_MASK 0x3
+#define PLL_POST_DIV_SHIFT 8
+#define PLL_POST_DIV_MASK 0xf
+#define PLL_ALPHA_EN BIT(24)
+#define PLL_VCO_SHIFT 20
+#define PLL_VCO_MASK 0x3
#define PLL_USER_CTL_U 0x14
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2016-08-11 8:42 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-11 8:40 [PATCH v2 00/10] clk: qcom: PLL updates Rajendra Nayak
2016-08-11 8:40 ` [PATCH v2 01/10] clk: Fix inconsistencies in usage of data types Rajendra Nayak
2016-08-13 0:59 ` Stephen Boyd
2016-08-11 8:40 ` [PATCH v2 02/10] clk: qcom: Add support for alpha pll hwfsm ops Rajendra Nayak
2016-08-24 6:13 ` Stephen Boyd
2016-08-25 9:05 ` Rajendra Nayak
2016-08-11 8:40 ` [PATCH v2 03/10] clk: qcom: Add support to initialize alpha plls Rajendra Nayak
2016-08-11 8:40 ` [PATCH v2 04/10] clk: qcom: Add support for PLLs with alpha mode Rajendra Nayak
2016-08-24 6:15 ` Stephen Boyd
2016-08-25 9:12 ` Rajendra Nayak
2016-08-11 8:40 ` [PATCH v2 05/10] clk: qcom: Add support for PLLs with early output Rajendra Nayak
2016-08-11 8:40 ` [PATCH v2 06/10] clk: qcom: Add support for PLLs supporting dynamic reprogramming Rajendra Nayak
2016-08-11 8:40 ` [PATCH v2 07/10] clk: qcom: Add support to enable FSM mode for votable alpha PLLs Rajendra Nayak
2016-08-24 6:31 ` Stephen Boyd
2016-08-25 9:16 ` Rajendra Nayak
2016-08-11 8:40 ` Rajendra Nayak [this message]
2016-08-13 0:57 ` [PATCH v2 08/10] clk: qcom: Cleanup some macro defs Stephen Boyd
2016-08-11 8:40 ` [PATCH v2 09/10] clk: qcom: Add .is_enabled ops for clk-alpha-pll Rajendra Nayak
2016-08-24 6:28 ` Stephen Boyd
2016-08-25 9:15 ` Rajendra Nayak
2016-08-11 8:40 ` [PATCH v2 10/10] clk: qcom: Fix .set_rate to handle alpha PLLs w/wo dynamic update Rajendra Nayak
2016-08-24 6:26 ` Stephen Boyd
2016-08-25 9:13 ` Rajendra Nayak
2016-08-24 6:17 ` [PATCH v2 00/10] clk: qcom: PLL updates Stephen Boyd
2016-08-25 9:17 ` Rajendra Nayak
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