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From: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
To: qemu-ppc@nongnu.org, david@gibson.dropbear.id.au, rth@twiddle.net
Cc: qemu-devel@nongnu.org, nikunj@linux.vnet.ibm.com,
	benh@kernel.crashing.org
Subject: [Qemu-devel] [PATCH RESEND v2 16/17] target-ppc: improve stxvw4x implementation
Date: Mon, 12 Sep 2016 12:11:45 +0530	[thread overview]
Message-ID: <1473662506-27441-17-git-send-email-nikunj@linux.vnet.ibm.com> (raw)
In-Reply-To: <1473662506-27441-1-git-send-email-nikunj@linux.vnet.ibm.com>

Manipulate data and store 8bytes instead of 4bytes.

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
 target-ppc/translate/vsx-impl.inc.c | 27 +++++++++++++--------------
 1 file changed, 13 insertions(+), 14 deletions(-)

diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index caa6660..f2fc5f9 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -205,7 +205,8 @@ static void gen_stxvd2x(DisasContext *ctx)
 
 static void gen_stxvw4x(DisasContext *ctx)
 {
-    TCGv_i64 tmp;
+    TCGv_i64 xsh = cpu_vsrh(xS(ctx->opcode));
+    TCGv_i64 xsl = cpu_vsrl(xS(ctx->opcode));
     TCGv EA;
     if (unlikely(!ctx->vsx_enabled)) {
         gen_exception(ctx, POWERPC_EXCP_VSXU);
@@ -214,21 +215,19 @@ static void gen_stxvw4x(DisasContext *ctx)
     gen_set_access_type(ctx, ACCESS_INT);
     EA = tcg_temp_new();
     gen_addr_reg_index(ctx, EA);
-    tmp = tcg_temp_new_i64();
-
-    tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
-    gen_qemu_st32_i64(ctx, tmp, EA);
-    tcg_gen_addi_tl(EA, EA, 4);
-    gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
-
-    tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
-    tcg_gen_addi_tl(EA, EA, 4);
-    gen_qemu_st32_i64(ctx, tmp, EA);
-    tcg_gen_addi_tl(EA, EA, 4);
-    gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
 
+    if (ctx->le_mode) {
+        tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ);
+        tcg_gen_addi_tl(EA, EA, 8);
+        tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ);
+    } else {
+        gen_helper_bswap32x2(xsh, xsh);
+        tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_LEQ);
+        tcg_gen_addi_tl(EA, EA, 8);
+        gen_helper_bswap32x2(xsl, xsl);
+        tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_LEQ);
+    }
     tcg_temp_free(EA);
-    tcg_temp_free_i64(tmp);
 }
 
 #define MV_VSRW(name, tcgop1, tcgop2, target, source)           \
-- 
2.7.4

  parent reply	other threads:[~2016-09-12  6:42 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-09-12  6:41 [Qemu-devel] [PATCH RESEND v2 00/17] POWER9 TCG enablements - part4 Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 01/17] target-ppc: consolidate load operations Nikunj A Dadhania
2016-09-15  0:46   ` David Gibson
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 02/17] target-ppc: convert ld64 to use new macro Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 03/17] target-ppc: convert ld[16, 32, 64]ur " Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 04/17] target-ppc: consolidate store operations Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 05/17] target-ppc: convert st64 to use new macro Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 06/17] target-ppc: convert st[16, 32, 64]r " Nikunj A Dadhania
2016-09-15  0:48   ` David Gibson
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 07/17] target-ppc: consolidate load with reservation Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 08/17] target-ppc: move out stqcx impementation Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 09/17] target-ppc: consolidate store conditional Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 10/17] target-ppc: add xxspltib instruction Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 11/17] target-ppc: implement darn instruction Nikunj A Dadhania
2016-09-15  1:07   ` David Gibson
2016-09-15  6:40     ` Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 12/17] target-ppc: add lxsi[bw]zx instruction Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 13/17] target-ppc: add stxsi[bh]x instruction Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 14/17] target-ppc: improve lxvw4x implementation Nikunj A Dadhania
2016-09-15  1:20   ` David Gibson
2016-09-15  9:57     ` Nikunj A Dadhania
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 15/17] target-ppc: add lxvb16x and lxvh8x Nikunj A Dadhania
2016-09-15  1:41   ` David Gibson
2016-09-16  8:26     ` Nikunj A Dadhania
2016-09-12  6:41 ` Nikunj A Dadhania [this message]
2016-09-15  1:44   ` [Qemu-devel] [PATCH RESEND v2 16/17] target-ppc: improve stxvw4x implementation David Gibson
2016-09-12  6:41 ` [Qemu-devel] [PATCH RESEND v2 17/17] target-ppc: add stxvb16x and stxvh8x Nikunj A Dadhania
2016-09-15  1:46   ` David Gibson
2016-09-16  8:28     ` Nikunj A Dadhania
2016-09-12  7:19 ` [Qemu-devel] [PATCH RESEND v2 00/17] POWER9 TCG enablements - part4 no-reply
2016-09-15  0:56 ` David Gibson
2016-09-15  1:49   ` David Gibson

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