diff for duplicates of <1490466197-29163-9-git-send-email-leo.yan@linaro.org>
diff --git a/a/1.txt b/N1/1.txt
index 58ef8ac..a9f6b6a 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -14,7 +14,7 @@ index 470461d..467aa15 100644
};
};
+
-+ debug@f6590000 {
++ debug at f6590000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf6590000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
@@ -22,7 +22,7 @@ index 470461d..467aa15 100644
+ cpu = <&cpu0>;
+ };
+
-+ debug@f6592000 {
++ debug at f6592000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf6592000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
@@ -30,7 +30,7 @@ index 470461d..467aa15 100644
+ cpu = <&cpu1>;
+ };
+
-+ debug@f6594000 {
++ debug at f6594000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf6594000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
@@ -38,7 +38,7 @@ index 470461d..467aa15 100644
+ cpu = <&cpu2>;
+ };
+
-+ debug@f6596000 {
++ debug at f6596000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf6596000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
@@ -46,7 +46,7 @@ index 470461d..467aa15 100644
+ cpu = <&cpu3>;
+ };
+
-+ debug@f65d0000 {
++ debug at f65d0000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf65d0000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
@@ -54,7 +54,7 @@ index 470461d..467aa15 100644
+ cpu = <&cpu4>;
+ };
+
-+ debug@f65d2000 {
++ debug at f65d2000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf65d2000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
@@ -62,7 +62,7 @@ index 470461d..467aa15 100644
+ cpu = <&cpu5>;
+ };
+
-+ debug@f65d4000 {
++ debug at f65d4000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf65d4000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
@@ -70,7 +70,7 @@ index 470461d..467aa15 100644
+ cpu = <&cpu6>;
+ };
+
-+ debug@f65d6000 {
++ debug at f65d6000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf65d6000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
diff --git a/a/content_digest b/N1/content_digest
index e9d4216..48c7ada 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,7 +2,7 @@
"ref\0001490466197-29163-1-git-send-email-leo.yan\@linaro.org\0"
]
[
- "From\0Leo Yan <leo.yan\@linaro.org>\0"
+ "From\0leo.yan\@linaro.org (Leo Yan)\0"
]
[
"Subject\0[PATCH v5 8/9] arm64: dts: hi6220: register debug module\0"
@@ -11,32 +11,7 @@
"Date\0Sun, 26 Mar 2017 02:23:16 +0800\0"
]
[
- "To\0Jonathan Corbet <corbet\@lwn.net>",
- " Rob Herring <robh+dt\@kernel.org>",
- " Mark Rutland <mark.rutland\@arm.com>",
- " Wei Xu <xuwei5\@hisilicon.com>",
- " Catalin Marinas <catalin.marinas\@arm.com>",
- " Will Deacon <will.deacon\@arm.com>",
- " Andy Gross <andy.gross\@linaro.org>",
- " David Brown <david.brown\@linaro.org>",
- " Michael Turquette <mturquette\@baylibre.com>",
- " Stephen Boyd <sboyd\@codeaurora.org>",
- " Mathieu Poirier <mathieu.poirier\@linaro.org>",
- " Guodong Xu <guodong.xu\@linaro.org>",
- " John Stultz <john.stultz\@linaro.org>",
- " linux-doc\@vger.kernel.org",
- " linux-kernel\@vger.kernel.org",
- " devicetree\@vger.kernel.org",
- " linux-arm-kernel\@lists.infradead.org",
- " linux-arm-msm\@vger.kernel.org",
- " linux-soc\@vger.kernel.org",
- " linux-clk\@vger.kernel.org",
- " mike.leach\@linaro.org",
- " Suzuki.Poulose\@arm.com",
- " sudeep.holla\@arm.com\0"
-]
-[
- "Cc\0Leo Yan <leo.yan\@linaro.org>\0"
+ "To\0linux-arm-kernel\@lists.infradead.org\0"
]
[
"\0000:1\0"
@@ -61,7 +36,7 @@
" \t\t\t};\n",
" \t\t};\n",
"+\n",
- "+\t\tdebug\@f6590000 {\n",
+ "+\t\tdebug at f6590000 {\n",
"+\t\t\tcompatible = \"arm,coresight-cpu-debug\",\"arm,primecell\";\n",
"+\t\t\treg = <0 0xf6590000 0 0x1000>;\n",
"+\t\t\tclocks = <&sys_ctrl HI6220_DAPB_CLK>;\n",
@@ -69,7 +44,7 @@
"+\t\t\tcpu = <&cpu0>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tdebug\@f6592000 {\n",
+ "+\t\tdebug at f6592000 {\n",
"+\t\t\tcompatible = \"arm,coresight-cpu-debug\",\"arm,primecell\";\n",
"+\t\t\treg = <0 0xf6592000 0 0x1000>;\n",
"+\t\t\tclocks = <&sys_ctrl HI6220_DAPB_CLK>;\n",
@@ -77,7 +52,7 @@
"+\t\t\tcpu = <&cpu1>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tdebug\@f6594000 {\n",
+ "+\t\tdebug at f6594000 {\n",
"+\t\t\tcompatible = \"arm,coresight-cpu-debug\",\"arm,primecell\";\n",
"+\t\t\treg = <0 0xf6594000 0 0x1000>;\n",
"+\t\t\tclocks = <&sys_ctrl HI6220_DAPB_CLK>;\n",
@@ -85,7 +60,7 @@
"+\t\t\tcpu = <&cpu2>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tdebug\@f6596000 {\n",
+ "+\t\tdebug at f6596000 {\n",
"+\t\t\tcompatible = \"arm,coresight-cpu-debug\",\"arm,primecell\";\n",
"+\t\t\treg = <0 0xf6596000 0 0x1000>;\n",
"+\t\t\tclocks = <&sys_ctrl HI6220_DAPB_CLK>;\n",
@@ -93,7 +68,7 @@
"+\t\t\tcpu = <&cpu3>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tdebug\@f65d0000 {\n",
+ "+\t\tdebug at f65d0000 {\n",
"+\t\t\tcompatible = \"arm,coresight-cpu-debug\",\"arm,primecell\";\n",
"+\t\t\treg = <0 0xf65d0000 0 0x1000>;\n",
"+\t\t\tclocks = <&sys_ctrl HI6220_DAPB_CLK>;\n",
@@ -101,7 +76,7 @@
"+\t\t\tcpu = <&cpu4>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tdebug\@f65d2000 {\n",
+ "+\t\tdebug at f65d2000 {\n",
"+\t\t\tcompatible = \"arm,coresight-cpu-debug\",\"arm,primecell\";\n",
"+\t\t\treg = <0 0xf65d2000 0 0x1000>;\n",
"+\t\t\tclocks = <&sys_ctrl HI6220_DAPB_CLK>;\n",
@@ -109,7 +84,7 @@
"+\t\t\tcpu = <&cpu5>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tdebug\@f65d4000 {\n",
+ "+\t\tdebug at f65d4000 {\n",
"+\t\t\tcompatible = \"arm,coresight-cpu-debug\",\"arm,primecell\";\n",
"+\t\t\treg = <0 0xf65d4000 0 0x1000>;\n",
"+\t\t\tclocks = <&sys_ctrl HI6220_DAPB_CLK>;\n",
@@ -117,7 +92,7 @@
"+\t\t\tcpu = <&cpu6>;\n",
"+\t\t};\n",
"+\n",
- "+\t\tdebug\@f65d6000 {\n",
+ "+\t\tdebug at f65d6000 {\n",
"+\t\t\tcompatible = \"arm,coresight-cpu-debug\",\"arm,primecell\";\n",
"+\t\t\treg = <0 0xf65d6000 0 0x1000>;\n",
"+\t\t\tclocks = <&sys_ctrl HI6220_DAPB_CLK>;\n",
@@ -130,4 +105,4 @@
"2.7.4"
]
-6e12151d50a2aae5cf278950a88833a644d3614f3f90762110f8565e24528e02
+7651f50908bea5a3a6f4cbfc15f97525ed690d6f3cafba6c9a70d4ee9bda772b
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