From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CA74AC433E7 for ; Mon, 31 Aug 2020 15:10:12 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9FD3A207EA for ; Mon, 31 Aug 2020 15:10:12 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="oxU1FAWk" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728270AbgHaPKL (ORCPT ); Mon, 31 Aug 2020 11:10:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52022 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728152AbgHaPJr (ORCPT ); Mon, 31 Aug 2020 11:09:47 -0400 Received: from mail-lf1-x143.google.com (mail-lf1-x143.google.com [IPv6:2a00:1450:4864:20::143]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE5DFC061755 for ; Mon, 31 Aug 2020 08:09:46 -0700 (PDT) Received: by mail-lf1-x143.google.com with SMTP id y11so1414963lfl.5 for ; Mon, 31 Aug 2020 08:09:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=m+ousw4fXr79+y3y64jWSrgKPSzonc7IxBJ1mGORPXc=; b=oxU1FAWkMAdlZNofP3Lz0EkAx+ley9wg9Sx9jjQQ4URQ+XnKMUyalJ9n4R1ITqQNY8 zH8oWA2z44OCkJtwldUGo4AF8wC9aAadul21JlM4bgVWsrGzqhRlrf1ptBhtWXZMi3Eq OFV+dHajvGnbRLrgAX3DLD77kxYX2E1teXA/WpMbtfFS9VMBn312R9eiGCCaboCjr+ki e2UzaAk6tROAdQputt3xy4WQoiqqRDRav6pQ4Q2VNX3bBRAHPZZwelsgKvatj+VpX9+C kalDx6pnXBODp/P56GV5O9gwDFxXzsIKUrwNlzMqErWq4pHLuhHitVorXFJpCepq3c0f sqcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=m+ousw4fXr79+y3y64jWSrgKPSzonc7IxBJ1mGORPXc=; b=NmowKut3WmRoJ7JfbeMwuG4N3Z7gWWsQzgGvzrMopuM8+Hm3JfjjcNEeYsLEBHj69L ihwWzz9jMJd4xY/mV/U5FukGjMuT0Vc8SjCzusOW8klMZQ5J/dVeTJ2Ooy1TwVIX2+Hb 4lMpxQr7c1JTTJr1+MUKwJMaYIoSBbu6igp4b09dqRsFmjiWuEiUuMYeVsflipLxJINP ib1toOAPMDVQtSWqp9tjKbPxJJHIxorJvS3e/m5g2T+Xe1NuS3KHkQarHq5Wvxdu8NjW 9QjwqaGpChPFNXHuj8JTgXOuvJyo3N5F9TdXLQ41ya8lDJXtXOEqPzq5OCxe3u6JMWmJ LcQA== X-Gm-Message-State: AOAM53382/pgo5MZHjE3uHx6M+2NFEwEmni2+cea0IIydfNP4wFEmjRg Zxbj5IaGuQCeS4WdcQ477X1jIg== X-Google-Smtp-Source: ABdhPJzdInn/v+/RHibWaNevmUbn23GSxa4f5Tmg5SIRq9zj/nOaSGRUihEyUSP8g9u+sdBwql02tA== X-Received: by 2002:ac2:42c2:: with SMTP id n2mr894835lfl.117.1598886584936; Mon, 31 Aug 2020 08:09:44 -0700 (PDT) Received: from gilgamesh.semihalf.com (193-106-246-138.noc.fibertech.net.pl. [193.106.246.138]) by smtp.gmail.com with ESMTPSA id w6sm2034388lfn.73.2020.08.31.08.09.42 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 31 Aug 2020 08:09:43 -0700 (PDT) From: Grzegorz Jaszczyk To: tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, s-anna@ti.com Cc: grzegorz.jaszczyk@linaro.org, robh+dt@kernel.org, lee.jones@linaro.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, david@lechnology.com, praneeth@ti.com Subject: [RESEND PATCH v5 0/5] Add TI PRUSS Local Interrupt Controller IRQChip driver Date: Mon, 31 Aug 2020 17:09:13 +0200 Message-Id: <1598886558-16546-1-git-send-email-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.7.4 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi All, The following is a v4 version of the series [1-4] that adds an IRQChip driver for the local interrupt controller present within a Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) present on a number of TI SoCs including OMAP architecture based AM335x, AM437x, AM57xx SoCs, Keystone 2 architecture based 66AK2G SoCs, Davinci architecture based OMAP-L138/DA850 SoCs and the latest K3 architecture based AM65x and J721E SoCs. Please see the v1 cover-letter [1] for details about the features of this interrupt controller. More details can be found in any of the supported SoC TRMs. Eg: Chapter 30.1.6 of AM5728 TRM [5] Please see the individual patches for exact changes in each patch, following are the main changes from v4: - Update dt-binding description (no functional changes). - Use more meaningful define/variable names, drop redundant error messages, fix error handling in case of irq == 0 (patch #2). [1] https://patchwork.kernel.org/cover/11034561/ [2] https://patchwork.kernel.org/cover/11069749/ [3] https://patchwork.kernel.org/cover/11639055/ [4] https://patchwork.kernel.org/cover/11688727/ [5] http://www.ti.com/lit/pdf/spruhz6 Best regards Grzegorz David Lechner (1): irqchip/irq-pruss-intc: Implement irq_{get,set}_irqchip_state ops Grzegorz Jaszczyk (1): irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts Suman Anna (3): dt-bindings: irqchip: Add PRU-ICSS interrupt controller bindings irqchip/irq-pruss-intc: Add logic for handling reserved interrupts irqchip/irq-pruss-intc: Add support for ICSSG INTC on K3 SoCs .../interrupt-controller/ti,pruss-intc.yaml | 158 +++++ drivers/irqchip/Kconfig | 10 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-pruss-intc.c | 658 +++++++++++++++++++++ 4 files changed, 827 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml create mode 100644 drivers/irqchip/irq-pruss-intc.c -- 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3B15EC433E2 for ; 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[193.106.246.138]) by smtp.gmail.com with ESMTPSA id w6sm2034388lfn.73.2020.08.31.08.09.42 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 31 Aug 2020 08:09:43 -0700 (PDT) From: Grzegorz Jaszczyk To: tglx@linutronix.de, jason@lakedaemon.net, maz@kernel.org, s-anna@ti.com Subject: [RESEND PATCH v5 0/5] Add TI PRUSS Local Interrupt Controller IRQChip driver Date: Mon, 31 Aug 2020 17:09:13 +0200 Message-Id: <1598886558-16546-1-git-send-email-grzegorz.jaszczyk@linaro.org> X-Mailer: git-send-email 2.7.4 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200831_110949_011154_BE51C756 X-CRM114-Status: GOOD ( 16.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, grzegorz.jaszczyk@linaro.org, david@lechnology.com, praneeth@ti.com, linux-kernel@vger.kernel.org, robh+dt@kernel.org, linux-omap@vger.kernel.org, lee.jones@linaro.org, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi All, The following is a v4 version of the series [1-4] that adds an IRQChip driver for the local interrupt controller present within a Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) present on a number of TI SoCs including OMAP architecture based AM335x, AM437x, AM57xx SoCs, Keystone 2 architecture based 66AK2G SoCs, Davinci architecture based OMAP-L138/DA850 SoCs and the latest K3 architecture based AM65x and J721E SoCs. Please see the v1 cover-letter [1] for details about the features of this interrupt controller. More details can be found in any of the supported SoC TRMs. Eg: Chapter 30.1.6 of AM5728 TRM [5] Please see the individual patches for exact changes in each patch, following are the main changes from v4: - Update dt-binding description (no functional changes). - Use more meaningful define/variable names, drop redundant error messages, fix error handling in case of irq == 0 (patch #2). [1] https://patchwork.kernel.org/cover/11034561/ [2] https://patchwork.kernel.org/cover/11069749/ [3] https://patchwork.kernel.org/cover/11639055/ [4] https://patchwork.kernel.org/cover/11688727/ [5] http://www.ti.com/lit/pdf/spruhz6 Best regards Grzegorz David Lechner (1): irqchip/irq-pruss-intc: Implement irq_{get,set}_irqchip_state ops Grzegorz Jaszczyk (1): irqchip/irq-pruss-intc: Add a PRUSS irqchip driver for PRUSS interrupts Suman Anna (3): dt-bindings: irqchip: Add PRU-ICSS interrupt controller bindings irqchip/irq-pruss-intc: Add logic for handling reserved interrupts irqchip/irq-pruss-intc: Add support for ICSSG INTC on K3 SoCs .../interrupt-controller/ti,pruss-intc.yaml | 158 +++++ drivers/irqchip/Kconfig | 10 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-pruss-intc.c | 658 +++++++++++++++++++++ 4 files changed, 827 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml create mode 100644 drivers/irqchip/irq-pruss-intc.c -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel