From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC0BCC46466 for ; Tue, 6 Oct 2020 04:27:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 794EC20757 for ; Tue, 6 Oct 2020 04:27:09 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="lzgHnzMd" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726890AbgJFE1I (ORCPT ); Tue, 6 Oct 2020 00:27:08 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:47901 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725945AbgJFE1I (ORCPT ); Tue, 6 Oct 2020 00:27:08 -0400 X-UUID: 3183a9b802d14886b6c434936fa1fa91-20201006 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:MIME-Version:Content-Type:References:In-Reply-To:Date:CC:To:From:Subject:Message-ID; bh=F3q8g07MfBf3wWRXqT3A3dyLSwe2uEIEqVCHGrlInMs=; b=lzgHnzMd4LPi1c4revL5Qjp1cHT8mEqYc5bsGwxTfIWD2r9GKussY2Eiit11KUdBgZzoTulQOJUiY5E64t47U1LK0lcF6olSX3Isa/EpOvKuujLah63tLi1rpQLi/GfQIt8uPZYtaaIHw7crJNlyOYSa6qqOMl5VaO6DXAuoqv0=; X-UUID: 3183a9b802d14886b6c434936fa1fa91-20201006 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 439787702; Tue, 06 Oct 2020 12:26:47 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS32N2.mediatek.inc (172.27.4.72) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 6 Oct 2020 12:26:46 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 6 Oct 2020 12:26:44 +0800 Message-ID: <1601958405.26323.24.camel@mhfsdcap03> Subject: Re: [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU From: Yong Wu To: Krzysztof Kozlowski CC: Joerg Roedel , Matthias Brugger , Rob Herring , Robin Murphy , Will Deacon , Evan Green , Tomasz Figa , , , , , , , , Nicolas Boichat , , , , Greg Kroah-Hartman , Date: Tue, 6 Oct 2020 12:26:45 +0800 In-Reply-To: <20201002111014.GE6888@pi3> References: <20200930070647.10188-1-yong.wu@mediatek.com> <20200930070647.10188-7-yong.wu@mediatek.com> <20201002111014.GE6888@pi3> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 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bh=F3q8g07MfBf3wWRXqT3A3dyLSwe2uEIEqVCHGrlInMs=; b=lzgHnzMd4LPi1c4revL5Qjp1cHT8mEqYc5bsGwxTfIWD2r9GKussY2Eiit11KUdBgZzoTulQOJUiY5E64t47U1LK0lcF6olSX3Isa/EpOvKuujLah63tLi1rpQLi/GfQIt8uPZYtaaIHw7crJNlyOYSa6qqOMl5VaO6DXAuoqv0=; X-UUID: 3183a9b802d14886b6c434936fa1fa91-20201006 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 439787702; Tue, 06 Oct 2020 12:26:47 +0800 Received: from MTKCAS32.mediatek.inc (172.27.4.184) by MTKMBS32N2.mediatek.inc (172.27.4.72) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 6 Oct 2020 12:26:46 +0800 Received: from [10.17.3.153] (10.17.3.153) by MTKCAS32.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 6 Oct 2020 12:26:44 +0800 Message-ID: <1601958405.26323.24.camel@mhfsdcap03> Subject: Re: [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU From: Yong Wu To: Krzysztof Kozlowski Date: Tue, 6 Oct 2020 12:26:45 +0800 In-Reply-To: <20201002111014.GE6888@pi3> References: <20200930070647.10188-1-yong.wu@mediatek.com> <20200930070647.10188-7-yong.wu@mediatek.com> <20201002111014.GE6888@pi3> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 1485479E20C5DFD0AF7462D3F5BFACAB78FE123516FD431872321E09329134412000:8 X-MTK: N Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, kernel-team@android.com, Nicolas Boichat , srv_heupstream@mediatek.com, chao.hao@mediatek.com, Robin Murphy , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, Evan Green , Tomasz Figa , iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , ming-fan.chen@mediatek.com, anan.sun@mediatek.com, Will Deacon , linux-arm-kernel@lists.infradead.org X-BeenThere: iommu@lists.linux-foundation.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: Development issues for Linux IOMMU support List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" Hi Krzysztof, On Fri, 2020-10-02 at 13:10 +0200, Krzysztof Kozlowski wrote: > On Wed, Sep 30, 2020 at 03:06:29PM +0800, Yong Wu wrote: > > This patch adds decriptions for mt8192 IOMMU and SMI. > > > > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation > > table format. The M4U-SMI HW diagram is as below: > > > > EMI > > | > > M4U > > | > > ------------ > > SMI Common > > ------------ > > | > > +-------+------+------+----------------------+-------+ > > | | | | ...... | | > > | | | | | | > > larb0 larb1 larb2 larb4 ...... larb19 larb20 > > disp0 disp1 mdp vdec IPE IPE > > > > All the connections are HW fixed, SW can NOT adjust it. > > > > mt8192 M4U support 0~16GB iova range. we preassign different engines > > into different iova ranges: > > > > domain-id module iova-range larbs > > 0 disp 0 ~ 4G larb0/1 > > 1 vcodec 4G ~ 8G larb4/5/7 > > 2 cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20 > > 3 CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10 > > 4 CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5 > > > > The iova range for CCU0/1(camera control unit) is HW requirement. > > > > Signed-off-by: Yong Wu > > Reviewed-by: Rob Herring > > --- > > .../bindings/iommu/mediatek,iommu.yaml | 9 +- > > .../mediatek,smi-common.yaml | 5 +- > > .../memory-controllers/mediatek,smi-larb.yaml | 3 +- > > include/dt-bindings/memory/mt8192-larb-port.h | 239 ++++++++++++++++++ > > 4 files changed, 251 insertions(+), 5 deletions(-) > > create mode 100644 include/dt-bindings/memory/mt8192-larb-port.h > > I see it depends on previous patches but does it have to be within one > commit? Is it not bisectable? The memory changes/bindings could go via > memory tree if this is split. Thanks for the view. I can split this into two patchset in next version, one is for iommu and the other is for smi. Only the patch [18/24] change both the code(iommu and smi). I don't plan to split it, and the smi patch[24/24] don't depend on it(won't conflict). since 18/24 also touch the smi code, I expect it could get Acked-by from you or Matthias, then Joerg could take it. Thanks. > > Best regards, > Krzysztof _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B7CAC46466 for ; Tue, 6 Oct 2020 04:27:21 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id AD5A020757 for ; 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Tue, 6 Oct 2020 12:26:44 +0800 Message-ID: <1601958405.26323.24.camel@mhfsdcap03> Subject: Re: [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU From: Yong Wu To: Krzysztof Kozlowski Date: Tue, 6 Oct 2020 12:26:45 +0800 In-Reply-To: <20201002111014.GE6888@pi3> References: <20200930070647.10188-1-yong.wu@mediatek.com> <20200930070647.10188-7-yong.wu@mediatek.com> <20201002111014.GE6888@pi3> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 1485479E20C5DFD0AF7462D3F5BFACAB78FE123516FD431872321E09329134412000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201006_002708_507181_3297108D X-CRM114-Status: GOOD ( 24.38 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, kernel-team@android.com, Nicolas Boichat , srv_heupstream@mediatek.com, chao.hao@mediatek.com, Robin Murphy , Joerg Roedel , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, Evan Green , Tomasz Figa , iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , ming-fan.chen@mediatek.com, anan.sun@mediatek.com, Will Deacon , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi Krzysztof, On Fri, 2020-10-02 at 13:10 +0200, Krzysztof Kozlowski wrote: > On Wed, Sep 30, 2020 at 03:06:29PM +0800, Yong Wu wrote: > > This patch adds decriptions for mt8192 IOMMU and SMI. > > > > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation > > table format. The M4U-SMI HW diagram is as below: > > > > EMI > > | > > M4U > > | > > ------------ > > SMI Common > > ------------ > > | > > +-------+------+------+----------------------+-------+ > > | | | | ...... | | > > | | | | | | > > larb0 larb1 larb2 larb4 ...... larb19 larb20 > > disp0 disp1 mdp vdec IPE IPE > > > > All the connections are HW fixed, SW can NOT adjust it. > > > > mt8192 M4U support 0~16GB iova range. we preassign different engines > > into different iova ranges: > > > > domain-id module iova-range larbs > > 0 disp 0 ~ 4G larb0/1 > > 1 vcodec 4G ~ 8G larb4/5/7 > > 2 cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20 > > 3 CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10 > > 4 CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5 > > > > The iova range for CCU0/1(camera control unit) is HW requirement. > > > > Signed-off-by: Yong Wu > > Reviewed-by: Rob Herring > > --- > > .../bindings/iommu/mediatek,iommu.yaml | 9 +- > > .../mediatek,smi-common.yaml | 5 +- > > .../memory-controllers/mediatek,smi-larb.yaml | 3 +- > > include/dt-bindings/memory/mt8192-larb-port.h | 239 ++++++++++++++++++ > > 4 files changed, 251 insertions(+), 5 deletions(-) > > create mode 100644 include/dt-bindings/memory/mt8192-larb-port.h > > I see it depends on previous patches but does it have to be within one > commit? Is it not bisectable? The memory changes/bindings could go via > memory tree if this is split. Thanks for the view. I can split this into two patchset in next version, one is for iommu and the other is for smi. Only the patch [18/24] change both the code(iommu and smi). I don't plan to split it, and the smi patch[24/24] don't depend on it(won't conflict). since 18/24 also touch the smi code, I expect it could get Acked-by from you or Matthias, then Joerg could take it. Thanks. > > Best regards, > Krzysztof _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,URIBL_BLOCKED, USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D857C41604 for ; Tue, 6 Oct 2020 04:28:33 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E4B0E20757 for ; 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Tue, 6 Oct 2020 12:26:44 +0800 Message-ID: <1601958405.26323.24.camel@mhfsdcap03> Subject: Re: [PATCH v3 06/24] dt-bindings: mediatek: Add binding for mt8192 IOMMU From: Yong Wu To: Krzysztof Kozlowski Date: Tue, 6 Oct 2020 12:26:45 +0800 In-Reply-To: <20201002111014.GE6888@pi3> References: <20200930070647.10188-1-yong.wu@mediatek.com> <20200930070647.10188-7-yong.wu@mediatek.com> <20201002111014.GE6888@pi3> X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 X-TM-SNTS-SMTP: 1485479E20C5DFD0AF7462D3F5BFACAB78FE123516FD431872321E09329134412000:8 X-MTK: N X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201006_002708_507181_3297108D X-CRM114-Status: GOOD ( 24.38 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: youlin.pei@mediatek.com, devicetree@vger.kernel.org, kernel-team@android.com, Nicolas Boichat , srv_heupstream@mediatek.com, chao.hao@mediatek.com, Robin Murphy , Joerg Roedel , Greg Kroah-Hartman , linux-kernel@vger.kernel.org, Evan Green , Tomasz Figa , iommu@lists.linux-foundation.org, Rob Herring , linux-mediatek@lists.infradead.org, Matthias Brugger , ming-fan.chen@mediatek.com, anan.sun@mediatek.com, Will Deacon , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Krzysztof, On Fri, 2020-10-02 at 13:10 +0200, Krzysztof Kozlowski wrote: > On Wed, Sep 30, 2020 at 03:06:29PM +0800, Yong Wu wrote: > > This patch adds decriptions for mt8192 IOMMU and SMI. > > > > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation > > table format. The M4U-SMI HW diagram is as below: > > > > EMI > > | > > M4U > > | > > ------------ > > SMI Common > > ------------ > > | > > +-------+------+------+----------------------+-------+ > > | | | | ...... | | > > | | | | | | > > larb0 larb1 larb2 larb4 ...... larb19 larb20 > > disp0 disp1 mdp vdec IPE IPE > > > > All the connections are HW fixed, SW can NOT adjust it. > > > > mt8192 M4U support 0~16GB iova range. we preassign different engines > > into different iova ranges: > > > > domain-id module iova-range larbs > > 0 disp 0 ~ 4G larb0/1 > > 1 vcodec 4G ~ 8G larb4/5/7 > > 2 cam/mdp 8G ~ 12G larb2/9/11/13/14/16/17/18/19/20 > > 3 CCU0 0x4000_0000 ~ 0x43ff_ffff larb13: port 9/10 > > 4 CCU1 0x4400_0000 ~ 0x47ff_ffff larb14: port 4/5 > > > > The iova range for CCU0/1(camera control unit) is HW requirement. > > > > Signed-off-by: Yong Wu > > Reviewed-by: Rob Herring > > --- > > .../bindings/iommu/mediatek,iommu.yaml | 9 +- > > .../mediatek,smi-common.yaml | 5 +- > > .../memory-controllers/mediatek,smi-larb.yaml | 3 +- > > include/dt-bindings/memory/mt8192-larb-port.h | 239 ++++++++++++++++++ > > 4 files changed, 251 insertions(+), 5 deletions(-) > > create mode 100644 include/dt-bindings/memory/mt8192-larb-port.h > > I see it depends on previous patches but does it have to be within one > commit? Is it not bisectable? The memory changes/bindings could go via > memory tree if this is split. Thanks for the view. I can split this into two patchset in next version, one is for iommu and the other is for smi. Only the patch [18/24] change both the code(iommu and smi). I don't plan to split it, and the smi patch[24/24] don't depend on it(won't conflict). since 18/24 also touch the smi code, I expect it could get Acked-by from you or Matthias, then Joerg could take it. Thanks. > > Best regards, > Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel