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From: Sibi Sankar <sibis@codeaurora.org>
To: sboyd@kernel.org, bjorn.andersson@linaro.org, robh+dt@kernel.org,
	mka@chromium.org
Cc: viresh.kumar@linaro.org, agross@kernel.org, rjw@rjwysocki.net,
	linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org,
	dianders@chromium.org, tdas@codeaurora.org,
	Sibi Sankar <sibis@codeaurora.org>
Subject: [PATCH 1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350
Date: Thu, 29 Jul 2021 23:34:42 +0530	[thread overview]
Message-ID: <1627581885-32165-2-git-send-email-sibis@codeaurora.org> (raw)
In-Reply-To: <1627581885-32165-1-git-send-email-sibis@codeaurora.org>

Re-arranging the register regions to support per core L3 DCVS would lead
to bindings breakage when using an older dt with a newer kernel. So,
document the EPSS compatible for SM8250/SM8350 SoCs and use them in the
CPUFreq-hw driver to prevent such breakages.

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
 Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt
index 9299028ee712..ee52fd8d3c9a 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.txt
@@ -8,7 +8,11 @@ Properties:
 - compatible
 	Usage:		required
 	Value type:	<string>
-	Definition:	must be "qcom,cpufreq-hw" or "qcom,cpufreq-epss".
+	Definition:	must be one of:
+			"qcom,cpufreq-epss"
+			"qcom,cpufreq-hw"
+			"qcom,sm8250-cpufreq-epss"
+			"qcom,sm8350-cpufreq-epss"
 
 - clocks
 	Usage:		required
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


  reply	other threads:[~2021-07-29 18:05 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-07-29 18:04 [PATCH 0/4] Fixup register offsets to support per core L3 DCVS Sibi Sankar
2021-07-29 18:04 ` Sibi Sankar [this message]
2021-08-03 19:23   ` [PATCH 1/4] dt-bindings: cpufreq: cpufreq-qcom-hw: Add compatible for SM8250/8350 Rob Herring
2021-08-04 18:56   ` Stephen Boyd
2021-07-29 18:04 ` [PATCH 2/4] cpufreq: qcom: Re-arrange register offsets to support per core L3 DCVS Sibi Sankar
2021-08-04 19:01   ` Stephen Boyd
2021-08-05 17:47     ` Sibi Sankar
2021-08-05 18:25       ` Stephen Boyd
2021-08-06  6:42         ` Sibi Sankar
2021-08-04 23:11   ` Bjorn Andersson
2021-08-04 23:20     ` Bjorn Andersson
2021-07-29 18:04 ` [PATCH 3/4] arm64: dts: qcom: sc7280: Fixup the cpufreq node Sibi Sankar
2021-08-04 18:57   ` Stephen Boyd
2021-08-31 15:30   ` Matthias Kaehlcke
2021-08-31 17:04     ` Bjorn Andersson
2021-09-06  3:20       ` Sibi Sankar
2021-09-07 19:14         ` Doug Anderson
2021-07-29 18:04 ` [PATCH 4/4] arm64: dts: qcom: sm8350: " Sibi Sankar
2021-08-04 22:59   ` Bjorn Andersson
2021-08-04 23:58     ` Matthias Kaehlcke
2021-08-30  6:47       ` Sibi Sankar

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