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From: Patchwork <patchwork@emeril.freedesktop.org>
To: "Ville Syrjala" <ville.syrjala@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings prep work (rev4)
Date: Wed, 29 Sep 2021 17:34:25 -0000	[thread overview]
Message-ID: <163293686520.27099.698335828379614624@emeril.freedesktop.org> (raw)
In-Reply-To: <20210927182455.27119-1-ville.syrjala@linux.intel.com>

== Series Details ==

Series: drm/i915: DP per-lane drive settings prep work (rev4)
URL   : https://patchwork.freedesktop.org/series/95122/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
5ca7aed58062 drm/i915: s/ddi_translations/trans/
-:1809: WARNING:LONG_LINE: line length of 102 exceeds 100 columns
#1809: FILE: drivers/gpu/drm/i915/display/intel_snps_phy.c:73:
+		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_PRE, trans->entries[level].snps.snps_pre_cursor);

-:1810: WARNING:LONG_LINE: line length of 104 exceeds 100 columns
#1810: FILE: drivers/gpu/drm/i915/display/intel_snps_phy.c:74:
+		val |= REG_FIELD_PREP(SNPS_PHY_TX_EQ_POST, trans->entries[level].snps.snps_post_cursor);

total: 0 errors, 2 warnings, 0 checks, 1677 lines checked
12af5655d6e9 drm/i915: Generalize .set_signal_levels()
148ee4908c2b drm/i915: Nuke usless .set_signal_levels() wrappers
96ccc8d77127 drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels()
40be81462b60 drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level()
025b7bd7473d drm/i915: Nuke intel_ddi_hdmi_num_entries()
68f42730e749 drm/i915: Pass the lane to intel_ddi_level()
24cdd73489e8 drm/i915: Prepare link training for per-lane drive settings
-:95: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'train_set' - possible side-effects?
#95: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:423:
+#define _TRAIN_SET_VSWING_ARGS(train_set) \
+	((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \
+	(train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : ""

-:98: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#98: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:426:
+#define TRAIN_SET_VSWING_ARGS(train_set) \
+	_TRAIN_SET_VSWING_ARGS((train_set)[0]), \
+	_TRAIN_SET_VSWING_ARGS((train_set)[1]), \
+	_TRAIN_SET_VSWING_ARGS((train_set)[2]), \
+	_TRAIN_SET_VSWING_ARGS((train_set)[3])

-:98: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'train_set' - possible side-effects?
#98: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:426:
+#define TRAIN_SET_VSWING_ARGS(train_set) \
+	_TRAIN_SET_VSWING_ARGS((train_set)[0]), \
+	_TRAIN_SET_VSWING_ARGS((train_set)[1]), \
+	_TRAIN_SET_VSWING_ARGS((train_set)[2]), \
+	_TRAIN_SET_VSWING_ARGS((train_set)[3])

-:103: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'train_set' - possible side-effects?
#103: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:431:
+#define _TRAIN_SET_PREEMPH_ARGS(train_set) \
+	((train_set) & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT, \
+	(train_set) & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? "(max)" : ""

-:106: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#106: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:434:
+#define TRAIN_SET_PREEMPH_ARGS(train_set) \
+	_TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \
+	_TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \
+	_TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \
+	_TRAIN_SET_PREEMPH_ARGS((train_set)[3])

-:106: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'train_set' - possible side-effects?
#106: FILE: drivers/gpu/drm/i915/display/intel_dp_link_training.c:434:
+#define TRAIN_SET_PREEMPH_ARGS(train_set) \
+	_TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \
+	_TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \
+	_TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \
+	_TRAIN_SET_PREEMPH_ARGS((train_set)[3])

total: 2 errors, 0 warnings, 4 checks, 111 lines checked
def5bc2e3c93 drm/i915: Allow per-lane drive settings with LTTPRs



  parent reply	other threads:[~2021-09-29 17:34 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-27 18:24 [Intel-gfx] [PATCH 0/9] drm/i915: DP per-lane drive settings prep work Ville Syrjala
2021-09-27 18:24 ` [Intel-gfx] [PATCH 1/9] drm/i915: s/ddi_translations/trans/ Ville Syrjala
2021-09-29 16:59   ` Imre Deak
2021-09-27 18:24 ` [Intel-gfx] [PATCH 2/9] drm/i915: Generalize .set_signal_levels() Ville Syrjala
2021-09-29 19:17   ` Imre Deak
2021-09-30  7:33     ` Ville Syrjälä
2021-09-27 18:24 ` [Intel-gfx] [PATCH 3/9] drm/i915: Nuke usless .set_signal_levels() wrappers Ville Syrjala
2021-09-29 19:43   ` Imre Deak
2021-09-27 18:24 ` [Intel-gfx] [PATCH 4/9] drm/i915: De-wrapper bxt_ddi_phy_set_signal_levels() Ville Syrjala
2021-09-29 19:48   ` Imre Deak
2021-09-27 18:24 ` [Intel-gfx] [PATCH 5/9] drm/i915: Hoover the level>=n_entries WARN into intel_ddi_level() Ville Syrjala
2021-09-29 20:09   ` Imre Deak
2021-09-27 18:24 ` [Intel-gfx] [PATCH 6/9] drm/i915: Nuke intel_ddi_hdmi_num_entries() Ville Syrjala
2021-09-29 20:11   ` Imre Deak
2021-09-27 18:24 ` [Intel-gfx] [PATCH 7/9] drm/i915: Pass the lane to intel_ddi_level() Ville Syrjala
2021-09-29 20:14   ` Imre Deak
2021-09-27 18:24 ` [Intel-gfx] [PATCH 8/9] drm/i915: Prepare link training for per-lane drive settings Ville Syrjala
2021-09-28 21:22   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2021-09-29 16:54   ` [Intel-gfx] [PATCH v3 " Ville Syrjala
2021-09-29 20:26     ` Imre Deak
2021-09-30  7:07       ` Ville Syrjälä
2021-09-27 18:24 ` [Intel-gfx] [PATCH 9/9] drm/i915: Allow per-lane drive settings with LTTPRs Ville Syrjala
2021-09-29 16:55   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2021-09-29 20:27     ` Imre Deak
2021-09-27 20:15 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings prep work Patchwork
2021-09-27 20:16 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-27 20:44 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-28  1:25 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-28 21:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: DP per-lane drive settings prep work (rev2) Patchwork
2021-09-28 21:55 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-09-28 22:23 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-29  0:54 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-29 17:34 ` Patchwork [this message]
2021-09-29 17:35 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: DP per-lane drive settings prep work (rev4) Patchwork
2021-09-29 18:05 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-29 21:12 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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