On Friday 27 April 2012 14:35:01 Grant Likely wrote: > On Mon, 23 Apr 2012 18:18:13 -0400, Scott Jiang wrote: > > This can make sure last bit has been shifted out of register. > > > > Signed-off-by: Scott Jiang > > Okay, so I have a few issues about the way this series was > submitted, but I've gone ahead and applied them anyway to get them off > my plate since they look like bug fixes. > > The problem is that the commit text is far from complete. here's the original commit messages: commit b489d522f6445de7261f4e57a52b6abe24717450 Author: Sonic Zhang Date: Fri Aug 12 10:44:43 2011 +0800 bug[#6683] spi:spi_bfin5xx: SPI SSEL deasserted too early in soft irq mode. Should poll FIFO in last dummy pump_transfer. Signed-off-by: Sonic Zhang commit 6201ee95d78b555b656cda6fadb91c031f90408c Author: Sonic Zhang Date: Thu Aug 11 18:24:16 2011 +0800 bug[#6683] spi:spi_bfin5xx: SPI SSEL deasserted too early in soft irq mode. Poll the FIFO till it is empty before deassert SSEL in pump_transfers in soft irq mode. No polling is necessary in interrupt mode and error handling. Signed-off-by: Sonic Zhang and here's the referenced bug: https://blackfin.uclinux.org/gf/tracker/6683 and here's a logic analyzer showing the problem :) http://blackfin.uclinux.org/gf/forumthread/44481 -mike