All of lore.kernel.org
 help / color / mirror / Atom feed
From: Richard Yang <weiyang@linux.vnet.ibm.com>
To: Richard Yang <weiyang@linux.vnet.ibm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>, linux-pci@vger.kernel.org
Subject: Re: Does my understanding correct?
Date: Sat, 28 Apr 2012 15:21:26 +0800	[thread overview]
Message-ID: <20120428072126.GB25916@richard> (raw)
In-Reply-To: <20120428050127.GA25916@richard>

On Sat, Apr 28, 2012 at 01:01:27PM +0800, Richard Yang wrote:
>On Fri, Apr 27, 2012 at 08:17:48AM -0600, Bjorn Helgaas wrote:
>>On Fri, Apr 27, 2012 at 3:27 AM, Richard Yang
>><weiyang@linux.vnet.ibm.com> wrote:
>>
>>I assume your question relates to the Stratus ftServer topology.  If
>>so, the lspci details might clarify things.
>>
>Yes, my picture is a little bit related to your previous mail.
>While my intention is to find out how the physical world is represented
>in the kernel.
>
>Below is a typical topology in PCIe spec r3.0.
>
>                          +------------------+
>                          |                  |
>                          |      RC          |
>                          |       Bus#0      |                                     
>                          | -------------    |                                     
>                          |                  |                                     
>                          +-+-----+--------+-+                                     
>         00:0.0             |     |        |        00:02.0                 
> +---------+---------+      |     |        |       +------------+-------------+
> |                   +------+     |        +-------|  PCIe 2 PCI Bridge       |
> |   PCIe Endpoint   |            |                |                          |
> +-------------------+            |                |  Bus#2                   |
>                                  |                |  --------------          |
>                                  |                +-------+---------------+--+
>                                  |                        |            |       
>                                  |  00:01.0               |02:00.0     |02:01.0
>                     +------------+-------------+  +-------+------+ +---+-------+
>                     |                          |  |PCI dev       | |PCI dev    |
>                     |       Switch             |  |              | |           |
>                     |       Bus#1              |  |              | |           |
>                     |     ---------------      |  +--------------+ +-----------+
>                     |                          |                               
>                     +------------------------+-+                               
>                        |                       |                                      
>                        |                       |                                      
>                        | 01:00.0               | 01:01.0                                    
>              +---------+-------+      +--------+----------------+                    
>              |                 |      |                         |                     
>              | PCI Endpoint    |      |  PCIe Endpoint          |                     
>              |                 |      |                         |                     
>              |                 |      |                         |                     
>              +-----------------+      +-------------------------+                     
>
>Do you think the current assignment of bus number and pci_dev is
>correct?
>
BTW, if the chart is correct, 01:00.0 reprents Switch DownStream Port 
or the PCI Endpoint?
>
>>In that system, my understanding is that 03:01.0 is a downstream port,
>>not an upstream port.
>>
>>I think your picture is slightly misleading because PCIe links are not
>>buses; they're point-to-point links between two devices.  You've drawn
>>#3 and #5 as buses that can have several devices on them, which is not
>>really the case.  The link from a downstream port should lead to
>>exactly one device.
>>
>>That's one thing that's strange in the ftServer topology: apparently
>>there are *two* devices on bus 03: the 03:00.0 upstream port and the
>>03:01.0 downstream port.  I think 03:00.0 is the upstream port of a
>>PCIe switch, which is perfectly normal.  My understanding is that
>>03:01.0 is another *downstream* port that leads to several more
>>devices (USB, NIC, etc).
>>
>>Bjorn
>
>-- 
>Richard Yang
>Help you, Help me

-- 
Richard Yang
Help you, Help me


  reply	other threads:[~2012-04-28  7:21 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-04-27  9:27 Does my understanding correct? Richard Yang
2012-04-27 14:10 ` Jiang Liu
2012-04-27 15:55   ` Bjorn Helgaas
2012-04-27 14:17 ` Bjorn Helgaas
2012-04-28  5:01   ` Richard Yang
2012-04-28  7:21     ` Richard Yang [this message]
2012-04-30 15:56     ` Bjorn Helgaas
2012-05-02  6:24       ` Richard Yang
2012-05-02 14:59         ` Bjorn Helgaas
2012-05-02 21:05           ` Don Dutile
2012-05-03  6:21           ` Richard Yang
2012-05-03 16:39             ` Bjorn Helgaas
2012-05-04  2:11               ` Richard Yang
2012-05-06 15:21               ` Richard Yang
2012-05-07  3:00               ` Richard Yang
2012-04-28  8:21   ` Richard Yang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20120428072126.GB25916@richard \
    --to=weiyang@linux.vnet.ibm.com \
    --cc=bhelgaas@google.com \
    --cc=linux-pci@vger.kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.