From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: Re: [PATCH 05/10] drm/i915: extract intel_gpu_reset Date: Sun, 29 Apr 2012 18:03:58 -0700 Message-ID: <20120429180358.6e61f5e3@bwidawsk.net> References: <1335532667-10597-1-git-send-email-daniel.vetter@ffwll.ch> <1335532667-10597-5-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from cloud01.chad-versace.us (184-106-247-128.static.cloud-ips.com [184.106.247.128]) by gabe.freedesktop.org (Postfix) with ESMTP id 0318D9E92C for ; Sun, 29 Apr 2012 18:04:09 -0700 (PDT) In-Reply-To: <1335532667-10597-5-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Fri, 27 Apr 2012 15:17:42 +0200 Daniel Vetter wrote: > Slightly cleans up the code and could be useful for e.g. Ben > Widawsky's hw context patches. > > v2: New colours! > > Cc: Ben Widawsky Unfortunately, I have been unable to make use of this patch. In all my attempts, doing intel_gpu_reset (with nothing else) will result in the next operation causing a hangcheck anyway. I think we should dig a bit more into this before we both. > Signed-Off-by: Daniel Vetter > --- > drivers/gpu/drm/i915/i915_drv.c | 43 ++++++++++++++++++++++++-------------- > 1 files changed, 27 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index f5450bb..c4251a1 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -768,6 +768,29 @@ static int gen6_do_reset(struct drm_device *dev, u8 flags) > return ret; > } > > +static int intel_gpu_reset(struct drm_device *dev, u8 flags) > +{ > + int ret = -ENODEV; > + > + switch (INTEL_INFO(dev)->gen) { > + case 7: > + case 6: > + ret = gen6_do_reset(dev, flags); > + break; > + case 5: > + ret = ironlake_do_reset(dev, flags); > + break; > + case 4: > + ret = i965_do_reset(dev, flags); > + break; > + case 2: > + ret = i8xx_do_reset(dev, flags); > + break; > + } > + > + return ret; > +} > + > /** > * i915_reset - reset chip after a hang > * @dev: drm device to reset > @@ -798,23 +821,11 @@ int i915_reset(struct drm_device *dev, u8 flags) > i915_gem_reset(dev); > > ret = -ENODEV; > - if (get_seconds() - dev_priv->last_gpu_reset < 5) { > + if (get_seconds() - dev_priv->last_gpu_reset < 5) > DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); > - } else switch (INTEL_INFO(dev)->gen) { > - case 7: > - case 6: > - ret = gen6_do_reset(dev, flags); > - break; > - case 5: > - ret = ironlake_do_reset(dev, flags); > - break; > - case 4: > - ret = i965_do_reset(dev, flags); > - break; > - case 2: > - ret = i8xx_do_reset(dev, flags); > - break; > - } > + else > + ret = intel_gpu_reset(dev, flags); > + > dev_priv->last_gpu_reset = get_seconds(); > if (ret) { > DRM_ERROR("Failed to reset chip.\n");