Re: [PATCH 2/3] x86/flush_tlb: try flush_tlb_single one by one in flush_tlb_range

[Borislav Petkov <bp@amd64.org>]

On Wed, May 02, 2012 at 05:24:09PM +0800, Alex Shi wrote:
> For some of scenario, above equation can be modified as:
> (512 - X) * 100ns(assumed TLB refill cost) = X * 140ns(assumed invlpg cost)
> 
> When thread number less than cpu numbers, balance point can up to 1/2
> TLB entries.
> 
> When thread number is equal to cpu number with HT, on our SNB EP
> machine, the balance point is 1/16 TLB entries, on NHM EP machine,
> balance at 1/32. So, need to change FLUSHALL_BAR to 32.

Are you saying you want to have this setting per family?

Also, have you run your patches with other benchmarks beside your
microbenchmark, say kernbench, SPEC<something>, i.e. some other
multithreaded benchmark touching shared memory? Are you seeing any
improvement there?

> when thread number is bigger than cpu number, context switch eat all
> improvement. the memory access latency is same as unpatched kernel.

Also, how do you know in the kernel that the thread number is the number
of all threads touching this shared mmapped region - there could be
unrelated threads doing something else.

Thanks.

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