Re: [PATCH 3/3] drm/i915: Update primary planes after a GPU reset

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Fri, Feb 15, 2013 at 03:28:33PM +0000, Chris Wilson wrote:
> On Fri, Feb 15, 2013 at 05:07:46PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > GPU reset will drop all flips that are still in the ring. So after the
> > reset, call update_plane() for all CRTCs to make sure the primary
> > planes are scanning out from the correct buffer.
> > 
> > The base address update will also generate a FLIP_DONE interrupt, which
> > will complete any pending flips. That means user space will get its
> > page flip events and won't get stuck waiting for them.
> 
> Not for all generations.

Hmm OK those seem to be the ones with the pending flip status bit
(Gen4 and older?).

But can someone explain why on those platforms we also check the
vblank interrupt status bit before handling the page flip interrupt?

Also wtf is i965_irq_handler doing? Based on the code it seems to be
expecting the pending flip interrupt to happen when the CS executes the
instruction, and then it'll finish the page flip from the following
vblank irq. BSpec doesn't agree, and still maintains that the page flip
interrupt will be generated when the flip really completes. Even if the
hardware would work the way the code suggests, the code is racy if the
ISR is delayed a bit and ends up handling the previous vblank interrupt
and the following flip pending interrupt at the same time. We'd really
need to check the live flip pending status from the ISR to make it
work right.

> There's no harm in explicitly finishing the
> pageflip, and then the FLIP_DONE is just a normal spurious interrupt.

All right. I suppose I'll need to make that change.

-- 
Ville Syrjälä
Intel OTC