From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753090AbbC3Sbp (ORCPT ); Mon, 30 Mar 2015 14:31:45 -0400 Received: from metis.ext.pengutronix.de ([92.198.50.35]:47388 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752898AbbC3Sbo (ORCPT ); Mon, 30 Mar 2015 14:31:44 -0400 Date: Mon, 30 Mar 2015 20:31:38 +0200 From: Sascha Hauer To: Joe Perches Cc: Mike Turquette , Stephen Boyd , YH Chen , linux-kernel@vger.kernel.org, Henry Chen , linux-mediatek@lists.infradead.org, kernel@pengutronix.de, Matthias Brugger , Yingjoe Chen , Eddie Huang , linux-arm-kernel@lists.infradead.org, James Liao Subject: Re: [PATCH 2/6] clk: mediatek: Add initial common clock support for Mediatek SoCs. Message-ID: <20150330183138.GG9742@pengutronix.de> References: <1427737245-4064-1-git-send-email-s.hauer@pengutronix.de> <1427737245-4064-3-git-send-email-s.hauer@pengutronix.de> <1427738146.14276.20.camel@perches.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1427738146.14276.20.camel@perches.com> X-Sent-From: Pengutronix Hildesheim X-URL: http://www.pengutronix.de/ X-IRC: #ptxdist @freenode X-Accept-Language: de,en X-Accept-Content-Type: text/plain X-Uptime: 20:28:59 up 14 days, 6:20, 45 users, load average: 0.08, 0.12, 0.13 User-Agent: Mutt/1.5.21 (2010-09-15) X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c0 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Mar 30, 2015 at 10:55:46AM -0700, Joe Perches wrote: > On Mon, 2015-03-30 at 19:40 +0200, Sascha Hauer wrote: > > This patch adds common clock support for Mediatek SoCs, including plls, > > muxes and clock gates. > > trivia: > > > diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c > > > +static int mtk_cg_bit_is_cleared(struct clk_hw *hw) > > +{ > [] > > + return val == 0; > > +} > > + > > +static int mtk_cg_bit_is_set(struct clk_hw *hw) > > +{ > [] > > + return val != 0; > > +} > > These functions may be better returning a bool The return type of these functions is forced by function prototype in struct clk_ops. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | From mboxrd@z Thu Jan 1 00:00:00 1970 From: s.hauer@pengutronix.de (Sascha Hauer) Date: Mon, 30 Mar 2015 20:31:38 +0200 Subject: [PATCH 2/6] clk: mediatek: Add initial common clock support for Mediatek SoCs. In-Reply-To: <1427738146.14276.20.camel@perches.com> References: <1427737245-4064-1-git-send-email-s.hauer@pengutronix.de> <1427737245-4064-3-git-send-email-s.hauer@pengutronix.de> <1427738146.14276.20.camel@perches.com> Message-ID: <20150330183138.GG9742@pengutronix.de> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Mar 30, 2015 at 10:55:46AM -0700, Joe Perches wrote: > On Mon, 2015-03-30 at 19:40 +0200, Sascha Hauer wrote: > > This patch adds common clock support for Mediatek SoCs, including plls, > > muxes and clock gates. > > trivia: > > > diff --git a/drivers/clk/mediatek/clk-gate.c b/drivers/clk/mediatek/clk-gate.c > > > +static int mtk_cg_bit_is_cleared(struct clk_hw *hw) > > +{ > [] > > + return val == 0; > > +} > > + > > +static int mtk_cg_bit_is_set(struct clk_hw *hw) > > +{ > [] > > + return val != 0; > > +} > > These functions may be better returning a bool The return type of these functions is forced by function prototype in struct clk_ops. Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |