From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751898AbdH1Ocb (ORCPT ); Mon, 28 Aug 2017 10:32:31 -0400 Received: from mail-wm0-f52.google.com ([74.125.82.52]:34536 "EHLO mail-wm0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751190AbdH1O3V (ORCPT ); Mon, 28 Aug 2017 10:29:21 -0400 From: Jerome Brunet To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Jerome Brunet , linux-mmc@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Neil Armstrong Subject: [PATCH v3 01/13] mmc: meson-gx: initialize sane clk default before clock register Date: Mon, 28 Aug 2017 16:29:03 +0200 Message-Id: <20170828142915.27020-2-jbrunet@baylibre.com> X-Mailer: git-send-email 2.9.5 In-Reply-To: <20170828142915.27020-1-jbrunet@baylibre.com> References: <20170828142915.27020-1-jbrunet@baylibre.com> Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On boot, the clock divider value is 0 which is a weird unsupported value. For example, accessing the cfg register with this value set would crash the SoC. Previous change removed 0 as possible value for CCF but forgot to properly initialize the register before registering the clock. This leads to the CCF finding an illegal value, which it complains about. Initialize the register properly in a standalone patch so the fix can be picked up if necessary Fixes: d045fe8c27af ("mmc: meson-gx: remove CLK_DIVIDER_ALLOW_ZERO clock flag") Reported-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 8a74a048db88..d2de5c11cdce 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -339,6 +339,15 @@ static int meson_mmc_clk_init(struct meson_host *host) const char *clk_div_parents[1]; u32 clk_reg, cfg; + /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ + clk_reg = 0; + clk_reg |= CLK_ALWAYS_ON; + clk_reg |= CLK_DIV_MASK; + clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase); + clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase); + clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase); + writel(clk_reg, host->regs + SD_EMMC_CLOCK); + /* get the mux parents */ for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { struct clk *clk; @@ -393,16 +402,6 @@ static int meson_mmc_clk_init(struct meson_host *host) if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk))) return PTR_ERR(host->cfg_div_clk); - /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ - clk_reg = 0; - clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase); - clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase); - clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase); - clk_reg |= FIELD_PREP(CLK_SRC_MASK, CLK_SRC_XTAL); - clk_reg |= FIELD_PREP(CLK_DIV_MASK, CLK_DIV_MAX); - clk_reg &= ~CLK_ALWAYS_ON; - writel(clk_reg, host->regs + SD_EMMC_CLOCK); - /* Ensure clock starts in "auto" mode, not "always on" */ cfg = readl(host->regs + SD_EMMC_CFG); cfg &= ~CFG_CLK_ALWAYS_ON; -- 2.9.5 From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jerome Brunet Subject: [PATCH v3 01/13] mmc: meson-gx: initialize sane clk default before clock register Date: Mon, 28 Aug 2017 16:29:03 +0200 Message-ID: <20170828142915.27020-2-jbrunet@baylibre.com> References: <20170828142915.27020-1-jbrunet@baylibre.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20170828142915.27020-1-jbrunet@baylibre.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: Ulf Hansson , Kevin Hilman , Carlo Caione Cc: Neil Armstrong , linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Jerome Brunet List-Id: linux-mmc@vger.kernel.org On boot, the clock divider value is 0 which is a weird unsupported value. For example, accessing the cfg register with this value set would crash the SoC. Previous change removed 0 as possible value for CCF but forgot to properly initialize the register before registering the clock. This leads to the CCF finding an illegal value, which it complains about. Initialize the register properly in a standalone patch so the fix can be picked up if necessary Fixes: d045fe8c27af ("mmc: meson-gx: remove CLK_DIVIDER_ALLOW_ZERO clock flag") Reported-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 8a74a048db88..d2de5c11cdce 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -339,6 +339,15 @@ static int meson_mmc_clk_init(struct meson_host *host) const char *clk_div_parents[1]; u32 clk_reg, cfg; + /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ + clk_reg = 0; + clk_reg |= CLK_ALWAYS_ON; + clk_reg |= CLK_DIV_MASK; + clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase); + clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase); + clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase); + writel(clk_reg, host->regs + SD_EMMC_CLOCK); + /* get the mux parents */ for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { struct clk *clk; @@ -393,16 +402,6 @@ static int meson_mmc_clk_init(struct meson_host *host) if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk))) return PTR_ERR(host->cfg_div_clk); - /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ - clk_reg = 0; - clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase); - clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase); - clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase); - clk_reg |= FIELD_PREP(CLK_SRC_MASK, CLK_SRC_XTAL); - clk_reg |= FIELD_PREP(CLK_DIV_MASK, CLK_DIV_MAX); - clk_reg &= ~CLK_ALWAYS_ON; - writel(clk_reg, host->regs + SD_EMMC_CLOCK); - /* Ensure clock starts in "auto" mode, not "always on" */ cfg = readl(host->regs + SD_EMMC_CFG); cfg &= ~CFG_CLK_ALWAYS_ON; -- 2.9.5 From mboxrd@z Thu Jan 1 00:00:00 1970 From: jbrunet@baylibre.com (Jerome Brunet) Date: Mon, 28 Aug 2017 16:29:03 +0200 Subject: [PATCH v3 01/13] mmc: meson-gx: initialize sane clk default before clock register In-Reply-To: <20170828142915.27020-1-jbrunet@baylibre.com> References: <20170828142915.27020-1-jbrunet@baylibre.com> Message-ID: <20170828142915.27020-2-jbrunet@baylibre.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On boot, the clock divider value is 0 which is a weird unsupported value. For example, accessing the cfg register with this value set would crash the SoC. Previous change removed 0 as possible value for CCF but forgot to properly initialize the register before registering the clock. This leads to the CCF finding an illegal value, which it complains about. Initialize the register properly in a standalone patch so the fix can be picked up if necessary Fixes: d045fe8c27af ("mmc: meson-gx: remove CLK_DIVIDER_ALLOW_ZERO clock flag") Reported-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 8a74a048db88..d2de5c11cdce 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -339,6 +339,15 @@ static int meson_mmc_clk_init(struct meson_host *host) const char *clk_div_parents[1]; u32 clk_reg, cfg; + /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ + clk_reg = 0; + clk_reg |= CLK_ALWAYS_ON; + clk_reg |= CLK_DIV_MASK; + clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase); + clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase); + clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase); + writel(clk_reg, host->regs + SD_EMMC_CLOCK); + /* get the mux parents */ for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { struct clk *clk; @@ -393,16 +402,6 @@ static int meson_mmc_clk_init(struct meson_host *host) if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk))) return PTR_ERR(host->cfg_div_clk); - /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ - clk_reg = 0; - clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase); - clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase); - clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase); - clk_reg |= FIELD_PREP(CLK_SRC_MASK, CLK_SRC_XTAL); - clk_reg |= FIELD_PREP(CLK_DIV_MASK, CLK_DIV_MAX); - clk_reg &= ~CLK_ALWAYS_ON; - writel(clk_reg, host->regs + SD_EMMC_CLOCK); - /* Ensure clock starts in "auto" mode, not "always on" */ cfg = readl(host->regs + SD_EMMC_CFG); cfg &= ~CFG_CLK_ALWAYS_ON; -- 2.9.5 From mboxrd@z Thu Jan 1 00:00:00 1970 From: jbrunet@baylibre.com (Jerome Brunet) Date: Mon, 28 Aug 2017 16:29:03 +0200 Subject: [PATCH v3 01/13] mmc: meson-gx: initialize sane clk default before clock register In-Reply-To: <20170828142915.27020-1-jbrunet@baylibre.com> References: <20170828142915.27020-1-jbrunet@baylibre.com> Message-ID: <20170828142915.27020-2-jbrunet@baylibre.com> To: linus-amlogic@lists.infradead.org List-Id: linus-amlogic.lists.infradead.org On boot, the clock divider value is 0 which is a weird unsupported value. For example, accessing the cfg register with this value set would crash the SoC. Previous change removed 0 as possible value for CCF but forgot to properly initialize the register before registering the clock. This leads to the CCF finding an illegal value, which it complains about. Initialize the register properly in a standalone patch so the fix can be picked up if necessary Fixes: d045fe8c27af ("mmc: meson-gx: remove CLK_DIVIDER_ALLOW_ZERO clock flag") Reported-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/mmc/host/meson-gx-mmc.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c index 8a74a048db88..d2de5c11cdce 100644 --- a/drivers/mmc/host/meson-gx-mmc.c +++ b/drivers/mmc/host/meson-gx-mmc.c @@ -339,6 +339,15 @@ static int meson_mmc_clk_init(struct meson_host *host) const char *clk_div_parents[1]; u32 clk_reg, cfg; + /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ + clk_reg = 0; + clk_reg |= CLK_ALWAYS_ON; + clk_reg |= CLK_DIV_MASK; + clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase); + clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase); + clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase); + writel(clk_reg, host->regs + SD_EMMC_CLOCK); + /* get the mux parents */ for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) { struct clk *clk; @@ -393,16 +402,6 @@ static int meson_mmc_clk_init(struct meson_host *host) if (WARN_ON(PTR_ERR_OR_ZERO(host->cfg_div_clk))) return PTR_ERR(host->cfg_div_clk); - /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */ - clk_reg = 0; - clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, host->tp.core_phase); - clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, host->tp.tx_phase); - clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, host->tp.rx_phase); - clk_reg |= FIELD_PREP(CLK_SRC_MASK, CLK_SRC_XTAL); - clk_reg |= FIELD_PREP(CLK_DIV_MASK, CLK_DIV_MAX); - clk_reg &= ~CLK_ALWAYS_ON; - writel(clk_reg, host->regs + SD_EMMC_CLOCK); - /* Ensure clock starts in "auto" mode, not "always on" */ cfg = readl(host->regs + SD_EMMC_CFG); cfg &= ~CFG_CLK_ALWAYS_ON; -- 2.9.5