From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751637AbeFAJh0 (ORCPT ); Fri, 1 Jun 2018 05:37:26 -0400 Received: from mail.skyhub.de ([5.9.137.197]:39816 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750790AbeFAJhX (ORCPT ); Fri, 1 Jun 2018 05:37:23 -0400 Date: Fri, 1 Jun 2018 11:37:35 +0200 From: Borislav Petkov To: David Wang Cc: tony.luck@intel.com, mingo@redhat.com, tglx@linutronix.de, hpa@zytor.com, gregkh@linuxfoudation.org, x86@kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, brucechang@via-alliance.com, cooperyan@zhaoxin.com, qiyuanwang@zhaoxin.com, benjaminpan@viatech.com, lukelin@viacpu.com, timguo@zhaoxin.com Subject: Re: [PATCH] x86/mce: add CMCI support for Centaur CPUs Message-ID: <20180601093735.GG17783@nazgul.tnic> References: <1527737338-4036-1-git-send-email-davidwang@zhaoxin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1527737338-4036-1-git-send-email-davidwang@zhaoxin.com> User-Agent: Mutt/1.6.0 (2016-04-01) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, May 31, 2018 at 11:28:58AM +0800, David Wang wrote: > Newer Centaur support CMCI mechanism, which is compatible with INTEL CMCI. > > Signed-off-by: David Wang > --- > arch/x86/Kconfig | 12 ++++++++++++ > arch/x86/kernel/cpu/mcheck/mce.c | 6 ++++++ > 2 files changed, 18 insertions(+) > > diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig > index dda87a3..1adff5f 100644 > --- a/arch/x86/Kconfig > +++ b/arch/x86/Kconfig > @@ -1130,6 +1130,18 @@ config X86_MCE_AMD > Additional support for AMD specific MCE features such as > the DRAM Error Threshold. > > +config X86_MCE_CENTAUR > + def_bool y > + prompt "CENTAUR MCE features" > + depends on CPU_SUP_CENTAUR && X86_MCE_INTEL > + help > + Additional support for Centaur specific MCE features such as > + MCE broadcasting and CMCI support. > + New Centaur CPU support MCE broadcasting. > + New Centaur CPU support CMCI which is fully compliant with Intel CMCI. > + > + If unsure, say N here. > + > config X86_ANCIENT_MCE > bool "Support for old Pentium 5 / WinChip machine checks" > depends on X86_32 && X86_MCE > diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c > index cd76380..2ebafc7 100644 > --- a/arch/x86/kernel/cpu/mcheck/mce.c > +++ b/arch/x86/kernel/cpu/mcheck/mce.c > @@ -1727,6 +1727,7 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c) > } > } > > +#ifdef CONFIG_X86_MCE_CENTAUR > static void mce_centaur_feature_init(struct cpuinfo_x86 *c) > { > struct mca_config *cfg = &mca_cfg; > @@ -1740,7 +1741,12 @@ static void mce_centaur_feature_init(struct cpuinfo_x86 *c) > if (cfg->monarch_timeout < 0) > cfg->monarch_timeout = USEC_PER_SEC; > } > + mce_intel_feature_init(c); > + mce_adjust_timer = cmci_intel_adjust_timer; So far so good but above says "New Centaur CPU[s]" but you're calling mce_intel_feature_init() unconditionally here, for *all* centaur CPUs. Ditto for setting the CMCI handler. Also mce_intel_feature_init() does more things than init CMCI so I think you wanna limit that to only intel_init_cmci(). IOW, something like the hunk below. And frankly I'm not crazy about adding centaur code to mce_intel.c but since it is copying functionality, I think we should copy the sw support in the kernel too instead of adding a mce_centaur.c duplicate. For now at least... Thx. --- diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c index d05be307d081..77d8a9b996a6 100644 --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c @@ -506,8 +506,15 @@ static void intel_ppin_init(struct cpuinfo_x86 *c) void mce_intel_feature_init(struct cpuinfo_x86 *c) { - intel_init_thermal(c); intel_init_cmci(); + + /* + * Some Centaur variants support CMCI. + */ + if (c->x86_vendor == X86_VENDOR_CENTAUR) + return; + + intel_init_thermal(c); intel_init_lmce(); intel_ppin_init(c); } -- Regards/Gruss, Boris. ECO tip #101: Trim your mails when you reply. -- From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: x86/mce: add CMCI support for Centaur CPUs From: Borislav Petkov Message-Id: <20180601093735.GG17783@nazgul.tnic> Date: Fri, 1 Jun 2018 11:37:35 +0200 To: David Wang Cc: tony.luck@intel.com, mingo@redhat.com, tglx@linutronix.de, hpa@zytor.com, gregkh@linuxfoudation.org, x86@kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, brucechang@via-alliance.com, cooperyan@zhaoxin.com, qiyuanwang@zhaoxin.com, benjaminpan@viatech.com, lukelin@viacpu.com, timguo@zhaoxin.com List-ID: T24gVGh1LCBNYXkgMzEsIDIwMTggYXQgMTE6Mjg6NThBTSArMDgwMCwgRGF2aWQgV2FuZyB3cm90 ZToKPiBOZXdlciBDZW50YXVyIHN1cHBvcnQgQ01DSSBtZWNoYW5pc20sIHdoaWNoIGlzIGNvbXBh dGlibGUgd2l0aCBJTlRFTCBDTUNJLgo+IAo+IFNpZ25lZC1vZmYtYnk6IERhdmlkIFdhbmcgPGRh dmlkd2FuZ0B6aGFveGluLmNvbT4KPiAtLS0KPiAgYXJjaC94ODYvS2NvbmZpZyAgICAgICAgICAg ICAgICAgfCAxMiArKysrKysrKysrKysKPiAgYXJjaC94ODYva2VybmVsL2NwdS9tY2hlY2svbWNl LmMgfCAgNiArKysrKysKPiAgMiBmaWxlcyBjaGFuZ2VkLCAxOCBpbnNlcnRpb25zKCspCj4gCj4g ZGlmZiAtLWdpdCBhL2FyY2gveDg2L0tjb25maWcgYi9hcmNoL3g4Ni9LY29uZmlnCj4gaW5kZXgg ZGRhODdhMy4uMWFkZmY1ZiAxMDA2NDQKPiAtLS0gYS9hcmNoL3g4Ni9LY29uZmlnCj4gKysrIGIv YXJjaC94ODYvS2NvbmZpZwo+IEBAIC0xMTMwLDYgKzExMzAsMTggQEAgY29uZmlnIFg4Nl9NQ0Vf QU1ECj4gIAkgICBBZGRpdGlvbmFsIHN1cHBvcnQgZm9yIEFNRCBzcGVjaWZpYyBNQ0UgZmVhdHVy ZXMgc3VjaCBhcwo+ICAJICAgdGhlIERSQU0gRXJyb3IgVGhyZXNob2xkLgo+ICAKPiArY29uZmln IFg4Nl9NQ0VfQ0VOVEFVUgo+ICsJZGVmX2Jvb2wgeQo+ICsJcHJvbXB0ICJDRU5UQVVSIE1DRSBm ZWF0dXJlcyIKPiArCWRlcGVuZHMgb24gQ1BVX1NVUF9DRU5UQVVSICYmIFg4Nl9NQ0VfSU5URUwK PiArCWhlbHAKPiArCSAgIEFkZGl0aW9uYWwgc3VwcG9ydCBmb3IgQ2VudGF1ciBzcGVjaWZpYyBN Q0UgZmVhdHVyZXMgc3VjaCBhcwo+ICsJICAgTUNFIGJyb2FkY2FzdGluZyBhbmQgQ01DSSBzdXBw b3J0Lgo+ICsJICAgTmV3IENlbnRhdXIgQ1BVIHN1cHBvcnQgTUNFIGJyb2FkY2FzdGluZy4KPiAr CSAgIE5ldyBDZW50YXVyIENQVSBzdXBwb3J0IENNQ0kgd2hpY2ggaXMgZnVsbHkgY29tcGxpYW50 IHdpdGggSW50ZWwgQ01DSS4KPiArCj4gKwkgICBJZiB1bnN1cmUsIHNheSBOIGhlcmUuCj4gKwo+ ICBjb25maWcgWDg2X0FOQ0lFTlRfTUNFCj4gIAlib29sICJTdXBwb3J0IGZvciBvbGQgUGVudGl1 bSA1IC8gV2luQ2hpcCBtYWNoaW5lIGNoZWNrcyIKPiAgCWRlcGVuZHMgb24gWDg2XzMyICYmIFg4 Nl9NQ0UKPiBkaWZmIC0tZ2l0IGEvYXJjaC94ODYva2VybmVsL2NwdS9tY2hlY2svbWNlLmMgYi9h cmNoL3g4Ni9rZXJuZWwvY3B1L21jaGVjay9tY2UuYwo+IGluZGV4IGNkNzYzODAuLjJlYmFmYzcg MTAwNjQ0Cj4gLS0tIGEvYXJjaC94ODYva2VybmVsL2NwdS9tY2hlY2svbWNlLmMKPiArKysgYi9h cmNoL3g4Ni9rZXJuZWwvY3B1L21jaGVjay9tY2UuYwo+IEBAIC0xNzI3LDYgKzE3MjcsNyBAQCBz dGF0aWMgdm9pZCBfX21jaGVja19jcHVfaW5pdF9lYXJseShzdHJ1Y3QgY3B1aW5mb194ODYgKmMp Cj4gIAl9Cj4gIH0KPiAgCj4gKyNpZmRlZiBDT05GSUdfWDg2X01DRV9DRU5UQVVSCj4gIHN0YXRp YyB2b2lkIG1jZV9jZW50YXVyX2ZlYXR1cmVfaW5pdChzdHJ1Y3QgY3B1aW5mb194ODYgKmMpCj4g IHsKPiAgCXN0cnVjdCBtY2FfY29uZmlnICpjZmcgPSAmbWNhX2NmZzsKPiBAQCAtMTc0MCw3ICsx NzQxLDEyIEBAIHN0YXRpYyB2b2lkIG1jZV9jZW50YXVyX2ZlYXR1cmVfaW5pdChzdHJ1Y3QgY3B1 aW5mb194ODYgKmMpCj4gIAkJaWYgKGNmZy0+bW9uYXJjaF90aW1lb3V0IDwgMCkKPiAgCQkJY2Zn LT5tb25hcmNoX3RpbWVvdXQgPSBVU0VDX1BFUl9TRUM7Cj4gIAl9Cj4gKwltY2VfaW50ZWxfZmVh dHVyZV9pbml0KGMpOwo+ICsJbWNlX2FkanVzdF90aW1lciA9IGNtY2lfaW50ZWxfYWRqdXN0X3Rp bWVyOwoKU28gZmFyIHNvIGdvb2QgYnV0IGFib3ZlIHNheXMgIk5ldyBDZW50YXVyIENQVVtzXSIg YnV0IHlvdSdyZSBjYWxsaW5nCm1jZV9pbnRlbF9mZWF0dXJlX2luaXQoKSB1bmNvbmRpdGlvbmFs bHkgaGVyZSwgZm9yICphbGwqIGNlbnRhdXIgQ1BVcy4KRGl0dG8gZm9yIHNldHRpbmcgdGhlIENN Q0kgaGFuZGxlci4KCkFsc28gbWNlX2ludGVsX2ZlYXR1cmVfaW5pdCgpIGRvZXMgbW9yZSB0aGlu Z3MgdGhhbiBpbml0IENNQ0kgc28gSSB0aGluawp5b3Ugd2FubmEgbGltaXQgdGhhdCB0byBvbmx5 IGludGVsX2luaXRfY21jaSgpLiBJT1csIHNvbWV0aGluZyBsaWtlIHRoZQpodW5rIGJlbG93LgoK QW5kIGZyYW5rbHkgSSdtIG5vdCBjcmF6eSBhYm91dCBhZGRpbmcgY2VudGF1ciBjb2RlIHRvIG1j ZV9pbnRlbC5jIGJ1dApzaW5jZSBpdCBpcyBjb3B5aW5nIGZ1bmN0aW9uYWxpdHksIEkgdGhpbmsg d2Ugc2hvdWxkIGNvcHkgdGhlIHN3IHN1cHBvcnQKaW4gdGhlIGtlcm5lbCB0b28gaW5zdGVhZCBv ZiBhZGRpbmcgYSBtY2VfY2VudGF1ci5jIGR1cGxpY2F0ZS4gRm9yIG5vdwphdCBsZWFzdC4uLgoK VGh4LgoKZGlmZiAtLWdpdCBhL2FyY2gveDg2L2tlcm5lbC9jcHUvbWNoZWNrL21jZV9pbnRlbC5j IGIvYXJjaC94ODYva2VybmVsL2NwdS9tY2hlY2svbWNlX2ludGVsLmMKaW5kZXggZDA1YmUzMDdk MDgxLi43N2Q4YTliOTk2YTYgMTAwNjQ0Ci0tLSBhL2FyY2gveDg2L2tlcm5lbC9jcHUvbWNoZWNr L21jZV9pbnRlbC5jCisrKyBiL2FyY2gveDg2L2tlcm5lbC9jcHUvbWNoZWNrL21jZV9pbnRlbC5j CkBAIC01MDYsOCArNTA2LDE1IEBAIHN0YXRpYyB2b2lkIGludGVsX3BwaW5faW5pdChzdHJ1Y3Qg Y3B1aW5mb194ODYgKmMpCiAKIHZvaWQgbWNlX2ludGVsX2ZlYXR1cmVfaW5pdChzdHJ1Y3QgY3B1 aW5mb194ODYgKmMpCiB7Ci0JaW50ZWxfaW5pdF90aGVybWFsKGMpOwogCWludGVsX2luaXRfY21j aSgpOworCisJLyoKKwkgKiBTb21lIENlbnRhdXIgdmFyaWFudHMgc3VwcG9ydCBDTUNJLgorCSAq LworCWlmIChjLT54ODZfdmVuZG9yID09IFg4Nl9WRU5ET1JfQ0VOVEFVUikKKwkJcmV0dXJuOwor CisJaW50ZWxfaW5pdF90aGVybWFsKGMpOwogCWludGVsX2luaXRfbG1jZSgpOwogCWludGVsX3Bw aW5faW5pdChjKTsKIH0K