From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59270) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1gDJFn-0004sL-HD for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:07:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1gDJFj-0003LM-Sq for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:07:03 -0400 Received: from out5-smtp.messagingengine.com ([66.111.4.29]:54903) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1gDJFj-00032s-Af for qemu-devel@nongnu.org; Thu, 18 Oct 2018 21:06:59 -0400 From: "Emilio G. Cota" Date: Thu, 18 Oct 2018 21:06:06 -0400 Message-Id: <20181019010625.25294-38-cota@braap.org> In-Reply-To: <20181019010625.25294-1-cota@braap.org> References: <20181019010625.25294-1-cota@braap.org> Subject: [Qemu-devel] [RFC v3 37/56] mips: convert to cpu_interrupt_request List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Aurelien Jarno , Aleksandar Markovic , James Hogan Cc: Aurelien Jarno Cc: Aleksandar Markovic Cc: James Hogan Signed-off-by: Emilio G. Cota --- target/mips/cpu.c | 6 +++--- target/mips/kvm.c | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 497706b669..e30aec6851 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -60,7 +60,7 @@ static bool mips_cpu_has_work(CPUState *cs) /* Prior to MIPS Release 6 it is implementation dependent if non-enabled interrupts wake-up the CPU, however most of the implementations only check for interrupts that can be taken. */ - if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && + if ((cpu_interrupt_request(cs) & CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { if (cpu_mips_hw_interrupts_enabled(env) || (env->insn_flags & ISA_MIPS32R6)) { @@ -72,7 +72,7 @@ static bool mips_cpu_has_work(CPUState *cs) if (env->CP0_Config3 & (1 << CP0C3_MT)) { /* The QEMU model will issue an _WAKE request whenever the CPUs should be woken up. */ - if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { + if (cpu_interrupt_request(cs) & CPU_INTERRUPT_WAKE) { has_work = true; } @@ -82,7 +82,7 @@ static bool mips_cpu_has_work(CPUState *cs) } /* MIPS Release 6 has the ability to halt the CPU. */ if (env->CP0_Config5 & (1 << CP0C5_VP)) { - if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { + if (cpu_interrupt_request(cs) & CPU_INTERRUPT_WAKE) { has_work = true; } if (!mips_vp_active(env)) { diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 0b177a7577..568c3d8f4a 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -135,7 +135,7 @@ void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) qemu_mutex_lock_iothread(); - if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && + if ((cpu_interrupt_request(cs) & CPU_INTERRUPT_HARD) && cpu_mips_io_interrupts_pending(cpu)) { intr.cpu = -1; intr.irq = 2; -- 2.17.1