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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 1/2] drm/i915: Turn dram_info.num_channels into a bitmask
Date: Wed, 20 Mar 2019 23:46:34 +0200	[thread overview]
Message-ID: <20190320214635.27814-1-ville.syrjala@linux.intel.com> (raw)

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We want to know out which channels are actually occupied so that
later on we can read the memory timings from the right registers.
To that end convert num_channels into a bitmask.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 28 +++++++++++++++-------------
 drivers/gpu/drm/i915/i915_drv.h |  2 +-
 2 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9e380cd317dc..8b37ec0e0676 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1209,14 +1209,14 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
 	val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
 	ret = skl_dram_get_channel_info(dev_priv, &ch0, 0, val);
 	if (ret == 0)
-		dram_info->num_channels++;
+		dram_info->channels |= BIT(0);
 
 	val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
 	ret = skl_dram_get_channel_info(dev_priv, &ch1, 1, val);
 	if (ret == 0)
-		dram_info->num_channels++;
+		dram_info->channels |= BIT(1);
 
-	if (dram_info->num_channels == 0) {
+	if (dram_info->channels == 0) {
 		DRM_INFO("Number of memory channels is zero\n");
 		return -EINVAL;
 	}
@@ -1285,8 +1285,8 @@ skl_get_dram_info(struct drm_i915_private *dev_priv)
 	mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
 				    SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
 
-	dram_info->bandwidth_kbps = dram_info->num_channels *
-							mem_freq_khz * 8;
+	dram_info->bandwidth_kbps = mem_freq_khz *
+		hweight8(dram_info->channels) * 8;
 
 	if (dram_info->bandwidth_kbps == 0) {
 		DRM_INFO("Couldn't get system memory bandwidth\n");
@@ -1380,20 +1380,20 @@ static int
 bxt_get_dram_info(struct drm_i915_private *dev_priv)
 {
 	struct dram_info *dram_info = &dev_priv->dram_info;
-	u32 dram_channels;
 	u32 mem_freq_khz, val;
-	u8 num_active_channels;
+	u8 num_channels = 0;
 	int i;
 
 	val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
 	mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
 				    BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
 
-	dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
-	num_active_channels = hweight32(dram_channels);
+	dram_info->channels = (val & BXT_DRAM_CHANNEL_ACTIVE_MASK) >>
+		BXT_DRAM_CHANNEL_ACTIVE_SHIFT;
 
 	/* Each active bit represents 4-byte channel */
-	dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
+	dram_info->bandwidth_kbps = mem_freq_khz *
+		hweight8(dram_info->channels) * 4;
 
 	if (dram_info->bandwidth_kbps == 0) {
 		DRM_INFO("Couldn't get system memory bandwidth\n");
@@ -1411,7 +1411,7 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
 		if (val == 0xFFFFFFFF)
 			continue;
 
-		dram_info->num_channels++;
+		num_channels++;
 
 		bxt_get_dimm_info(&dimm, val);
 		type = bxt_get_dimm_type(val);
@@ -1439,6 +1439,8 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
 			dram_info->type = type;
 	}
 
+	WARN_ON(num_channels != hweight8(dram_info->channels));
+
 	if (dram_info->type == INTEL_DRAM_UNKNOWN ||
 	    dram_info->ranks == 0) {
 		DRM_INFO("couldn't get memory information\n");
@@ -1472,9 +1474,9 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
 	if (ret)
 		return;
 
-	DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: %u\n",
+	DRM_DEBUG_KMS("DRAM bandwidth: %u kBps, channels: 0x%x\n",
 		      dram_info->bandwidth_kbps,
-		      dram_info->num_channels);
+		      dram_info->channels);
 
 	DRM_DEBUG_KMS("DRAM ranks: %u, 16Gb DIMMs: %s\n",
 		      dram_info->ranks, yesno(dram_info->is_16gb_dimm));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 363b2d3e4d50..f638c0c74955 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1832,7 +1832,7 @@ struct drm_i915_private {
 	struct dram_info {
 		bool valid;
 		bool is_16gb_dimm;
-		u8 num_channels;
+		u8 channels; /* bitmask */
 		u8 ranks;
 		u32 bandwidth_kbps;
 		bool symmetric_memory;
-- 
2.19.2

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             reply	other threads:[~2019-03-20 21:46 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-20 21:46 Ville Syrjala [this message]
2019-03-20 21:46 ` [PATCH 2/2] drm/i915: Make sure we have enough memory bandwidth on ICL Ville Syrjala
2019-03-21  9:34   ` Lisovskiy, Stanislav
2019-03-21 10:32     ` Ville Syrjälä
2019-03-22 17:04   ` Ville Syrjälä
2019-03-27 14:12   ` Maarten Lankhorst
2019-03-20 23:43 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask Patchwork
2019-03-20 23:44 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-03-21  0:12 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-03-21  5:24 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask (rev2) Patchwork
2019-03-21  5:25 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-03-21  5:53 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-03-21  6:12 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/i915: Turn dram_info.num_channels into a bitmask (rev3) Patchwork
2019-03-21  6:14 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-03-21  6:33 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-21  7:50   ` Saarinen, Jani
2019-03-21 13:36 ` ✗ Fi.CI.IGT: failure " Patchwork

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