From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([209.51.188.92]:40089) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hHkWU-0008NH-VX for qemu-devel@nongnu.org; Sat, 20 Apr 2019 03:34:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hHkWU-0007iN-0L for qemu-devel@nongnu.org; Sat, 20 Apr 2019 03:34:54 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:46119) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hHkWT-0007gn-Qr for qemu-devel@nongnu.org; Sat, 20 Apr 2019 03:34:53 -0400 Received: by mail-pl1-x642.google.com with SMTP id o7so1289443pll.13 for ; Sat, 20 Apr 2019 00:34:53 -0700 (PDT) From: Richard Henderson Date: Fri, 19 Apr 2019 21:34:08 -1000 Message-Id: <20190420073442.7488-5-richard.henderson@linaro.org> In-Reply-To: <20190420073442.7488-1-richard.henderson@linaro.org> References: <20190420073442.7488-1-richard.henderson@linaro.org> Subject: [Qemu-devel] [PATCH 04/38] tcg: Support cross-class moves without instruction support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: david@redhat.com PowerPC Altivec does not support direct moves between vector registers and general registers. So when tcg_out_mov fails, we can use the backing memory for the temporary to perform the move. Signed-off-by: Richard Henderson --- tcg/tcg.c | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index b083faacd2..d3dcfe3dca 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3373,7 +3373,18 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) ots->indirect_base); } if (!tcg_out_mov(s, otype, ots->reg, ts->reg)) { - abort(); + /* Cross register class move not supported. + Store the source register into the destination slot + and leave the destination temp as TEMP_VAL_MEM. */ + assert(!ots->fixed_reg); + if (!ts->mem_allocated) { + temp_allocate_frame(s, ots); + } + tcg_out_st(s, ts->type, ts->reg, + ots->mem_base->reg, ots->mem_offset); + ots->mem_coherent = 1; + temp_free_or_dead(s, ots, -1); + return; } } ots->val_type = TEMP_VAL_REG; @@ -3475,7 +3486,11 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, o_preferred_regs, ts->indirect_base); if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { - abort(); + /* Cross register class move not supported. Sync the + temp back to its slot and load from there. */ + temp_sync(s, ts, i_allocated_regs, 0, 0); + tcg_out_ld(s, ts->type, reg, + ts->mem_base->reg, ts->mem_offset); } } new_args[i] = reg; @@ -3634,7 +3649,11 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) if (ts->reg != reg) { tcg_reg_free(s, reg, allocated_regs); if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { - abort(); + /* Cross register class move not supported. Sync the + temp back to its slot and load from there. */ + temp_sync(s, ts, allocated_regs, 0, 0); + tcg_out_ld(s, ts->type, reg, + ts->mem_base->reg, ts->mem_offset); } } } else { -- 2.17.1