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From: Fernando Pacheco <fernando.pacheco@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [RFC PATCH 0/1] GuC engine reset support
Date: Wed, 25 Sep 2019 16:00:31 -0700	[thread overview]
Message-ID: <20190925230032.23676-1-fernando.pacheco@intel.com> (raw)

Another attempt at providing GuC a list of registers to
save/restore during engine resets [1].

The list we provide GuC should mirror, with possibly some exceptions,
the list of registers applied during execlists_resume/enable_execlists.
Any ideas on how to flag any discrepancies (yet flexible enough to
handle exceptions) between the two lists e.g. via a selftest? I would
like something stronger than a comment that just states the other needs
updating. Or should I take this to mean a different approach is needed?

Thanks,
Fernando

[1] https://patchwork.freedesktop.org/patch/161888/

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>

Fernando Pacheco (1):
  drm/i915/guc: Provide mmio list to be saved/restored on engine reset

 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 23 +++--
 .../gpu/drm/i915/gt/intel_workarounds_types.h |  1 +
 drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c    | 87 +++++++++++++++++++
 3 files changed, 105 insertions(+), 6 deletions(-)

-- 
2.23.0

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             reply	other threads:[~2019-09-25 23:05 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-09-25 23:00 Fernando Pacheco [this message]
2019-09-25 23:00 ` [RFC PATCH 1/1] drm/i915/guc: Provide mmio list to be saved/restored on engine reset Fernando Pacheco
2019-09-25 23:33 ` ✓ Fi.CI.BAT: success for GuC engine reset support Patchwork
2019-09-26 18:58 ` ✓ Fi.CI.IGT: " Patchwork

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