From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4037DC10F14 for ; Sun, 6 Oct 2019 17:42:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0C6BD2173B for ; Sun, 6 Oct 2019 17:42:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1570383738; bh=vNJVuAcZSGd4JfMJeT1HcCWqm+jXlfUf9xrhXZuLZQE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=WnvKKbo2ConYNCEPmvmxDoLGzbkYsgl41rVNDBiLX4RdQYWnfuph0LsdqFVcALvfl 2cd8qVlx/T/NtbvTUDNrHftnxrl/PC8Y+Yoy94/oW7hXo60JZae4B8/k+UDBcYTwdx pnqM/DXIHtVAigIyHyf7IpbIIDPuQKFUpASN0uIM= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731316AbfJFRmR (ORCPT ); Sun, 6 Oct 2019 13:42:17 -0400 Received: from mail.kernel.org ([198.145.29.99]:41914 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730875AbfJFRmK (ORCPT ); Sun, 6 Oct 2019 13:42:10 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id B246C2080F; Sun, 6 Oct 2019 17:42:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1570383730; bh=vNJVuAcZSGd4JfMJeT1HcCWqm+jXlfUf9xrhXZuLZQE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qm0GdRRIC/cTkdWZzFHKvMCNb3Q6IS1hqkjXo79IXXChjQnib9/f5T2eFfcaPet8a j1tOBFnMnVsDD7xn6n13kjUuth+Ys6o2QkhkaktjMl0mcdYJLCnfOt5KIa/nlpBb6j tRvJlEWQMdHY1SvpTDCQ1QYFKVRj2e8sX7z05ed0= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Leonard Crestez , Peng Fan , Stephen Boyd , Sasha Levin Subject: [PATCH 5.3 073/166] clk: imx: clk-pll14xx: unbypass PLL by default Date: Sun, 6 Oct 2019 19:20:39 +0200 Message-Id: <20191006171219.574571166@linuxfoundation.org> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191006171212.850660298@linuxfoundation.org> References: <20191006171212.850660298@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Peng Fan [ Upstream commit a9aa8306074d9519dd6e5fdf07240b01bac72e04 ] When registering the PLL, unbypass the PLL. The PLL has two bypass control bit, BYPASS and EXT_BYPASS. we will expose EXT_BYPASS to clk driver for mux usage, and keep BYPASS inside pll14xx usage. The PLL has a restriction that when M/P change, need to RESET/BYPASS pll to avoid glitch, so we could not expose BYPASS. To make it easy for clk driver usage, unbypass PLL which does not hurt current function. Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc") Reviewed-by: Leonard Crestez Signed-off-by: Peng Fan Link: https://lkml.kernel.org/r/1568043491-20680-3-git-send-email-peng.fan@nxp.com Signed-off-by: Stephen Boyd Signed-off-by: Sasha Levin --- drivers/clk/imx/clk-pll14xx.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/clk/imx/clk-pll14xx.c b/drivers/clk/imx/clk-pll14xx.c index 656f48b002dd3..7a815ec76aa5c 100644 --- a/drivers/clk/imx/clk-pll14xx.c +++ b/drivers/clk/imx/clk-pll14xx.c @@ -368,6 +368,7 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, struct clk_pll14xx *pll; struct clk *clk; struct clk_init_data init; + u32 val; pll = kzalloc(sizeof(*pll), GFP_KERNEL); if (!pll) @@ -399,6 +400,10 @@ struct clk *imx_clk_pll14xx(const char *name, const char *parent_name, pll->rate_table = pll_clk->rate_table; pll->rate_count = pll_clk->rate_count; + val = readl_relaxed(pll->base + GNRL_CTL); + val &= ~BYPASS_MASK; + writel_relaxed(val, pll->base + GNRL_CTL); + clk = clk_register(NULL, &pll->hw); if (IS_ERR(clk)) { pr_err("%s: failed to register pll %s %lu\n", -- 2.20.1