From mboxrd@z Thu Jan 1 00:00:00 1970 From: Simon Glass Date: Sun, 20 Oct 2019 21:38:30 -0600 Subject: [U-Boot] [PATCH v3 065/108] x86: Disable microcode section for FSP2 In-Reply-To: <20191021033913.220758-22-sjg@chromium.org> References: <20191021033913.220758-22-sjg@chromium.org> Message-ID: <20191020213517.v3.65.I9f8b22481950b80d46830a0bf034376ea97b564e@changeid> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de At present we don't support loading microcode with FSP2. The correct way to do this is by adding it to the FIT. For now, disable including microcode in the image. Signed-off-by: Simon Glass --- Changes in v3: - Drop unnecessary #else part of CONFIG_HAVE_MICROCODE Changes in v2: None arch/x86/Kconfig | 4 ++++ arch/x86/dts/u-boot.dtsi | 7 +++++++ 2 files changed, 11 insertions(+) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 69327bd746a..37e94d8913a 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -598,6 +598,10 @@ config HAVE_REFCODE broadwell) U-Boot will be missing some critical setup steps. Various peripherals may fail to work. +config HAVE_MICROCODE + bool + default y if !FSP_VERSION2 + config SMP bool "Enable Symmetric Multiprocessing" default n diff --git a/arch/x86/dts/u-boot.dtsi b/arch/x86/dts/u-boot.dtsi index 049f47c9ffd..aaca8874540 100644 --- a/arch/x86/dts/u-boot.dtsi +++ b/arch/x86/dts/u-boot.dtsi @@ -37,11 +37,13 @@ }; #endif #ifdef CONFIG_TPL +#ifdef CONFIG_HAVE_MICROCODE u-boot-tpl-with-ucode-ptr { offset = ; }; u-boot-tpl-dtb { }; +#endif u-boot-spl { offset = ; }; @@ -77,11 +79,16 @@ offset = ; }; #endif +#ifdef CONFIG_HAVE_MICROCODE u-boot-dtb-with-ucode { }; u-boot-ucode { align = <16>; }; +#else + u-boot-dtb { + }; +#endif #ifdef CONFIG_X86_HAS_FIT intel-fit { }; -- 2.23.0.866.gb869b98d4c-goog