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From: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Sunpeng.Li@amd.com, Bhawanpreet.Lakha@amd.com,
	Tony Cheng <Tony.Cheng@amd.com>,
	Harry Wentland <harry.wentland@amd.com>,
	Noah Abradjian <noah.abradjian@amd.com>
Subject: [PATCH 11/43] drm/amd/display: Add double buffering to dcn20 OCSC
Date: Fri, 10 Jan 2020 09:46:23 -0500	[thread overview]
Message-ID: <20200110144655.55845-12-Rodrigo.Siqueira@amd.com> (raw)
In-Reply-To: <20200110144655.55845-1-Rodrigo.Siqueira@amd.com>

From: Noah Abradjian <noah.abradjian@amd.com>

[Why]
When rapidly adjusting colour properties (e.g. brightness), screen tearing was observed.
This was due to overwritten values in OCSC registers. In dcn10, this issue had been fixed by
implementing double buffering by alternating OCSC modes.

[How]
Alternate which OCSC registers are used by switching modes each time.
This double buffers the CSC writes.

Signed-off-by: Noah Abradjian <noah.abradjian@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c  | 45 ++++++++++++++++---
 .../gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h  | 16 +++++++
 .../drm/amd/display/dc/dcn20/dcn20_resource.c |  1 +
 .../drm/amd/display/dc/dcn21/dcn21_resource.c |  3 +-
 4 files changed, 59 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
index f90031ed58a6..c38f7fdb43a8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.c
@@ -33,6 +33,9 @@
 #define REG(reg)\
 	mpc20->mpc_regs->reg
 
+#define IND_REG(index) \
+	(index)
+
 #define CTX \
 	mpc20->base.ctx
 
@@ -132,19 +135,32 @@ void mpc2_set_output_csc(
 		const uint16_t *regval,
 		enum mpc_output_csc_mode ocsc_mode)
 {
+	uint32_t cur_mode;
 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
 	struct color_matrices_reg ocsc_regs;
 
-	REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
-
-	if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE)
+	if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) {
+		REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
 		return;
+	}
 
 	if (regval == NULL) {
 		BREAK_TO_DEBUGGER();
 		return;
 	}
 
+	/* determine which CSC coefficients (A or B) we are using
+	 * currently.  select the alternate set to double buffer
+	 * the CSC update so CSC is updated on frame boundary
+	 */
+	cur_mode = IX_REG_READ(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_DATA,
+						MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE_IDX);
+
+	if (cur_mode != MPC_OUTPUT_CSC_COEF_A)
+		ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
+	else
+		ocsc_mode = MPC_OUTPUT_CSC_COEF_B;
+
 	ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A;
 	ocsc_regs.masks.csc_c11  = mpc20->mpc_mask->MPC_OCSC_C11_A;
 	ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A;
@@ -157,10 +173,13 @@ void mpc2_set_output_csc(
 		ocsc_regs.csc_c11_c12 = REG(CSC_C11_C12_B[opp_id]);
 		ocsc_regs.csc_c33_c34 = REG(CSC_C33_C34_B[opp_id]);
 	}
+
 	cm_helper_program_color_matrices(
 			mpc20->base.ctx,
 			regval,
 			&ocsc_regs);
+
+	REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
 }
 
 void mpc2_set_ocsc_default(
@@ -169,14 +188,16 @@ void mpc2_set_ocsc_default(
 		enum dc_color_space color_space,
 		enum mpc_output_csc_mode ocsc_mode)
 {
+	uint32_t cur_mode;
 	struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
 	uint32_t arr_size;
 	struct color_matrices_reg ocsc_regs;
 	const uint16_t *regval = NULL;
 
-	REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
-	if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE)
+	if (ocsc_mode == MPC_OUTPUT_CSC_DISABLE) {
+		REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
 		return;
+	}
 
 	regval = find_color_matrix(color_space, &arr_size);
 
@@ -185,6 +206,18 @@ void mpc2_set_ocsc_default(
 		return;
 	}
 
+	/* determine which CSC coefficients (A or B) we are using
+	 * currently.  select the alternate set to double buffer
+	 * the CSC update so CSC is updated on frame boundary
+	 */
+	cur_mode = IX_REG_READ(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_DATA,
+						MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE_IDX);
+
+	if (cur_mode != MPC_OUTPUT_CSC_COEF_A)
+		ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
+	else
+		ocsc_mode = MPC_OUTPUT_CSC_COEF_B;
+
 	ocsc_regs.shifts.csc_c11 = mpc20->mpc_shift->MPC_OCSC_C11_A;
 	ocsc_regs.masks.csc_c11  = mpc20->mpc_mask->MPC_OCSC_C11_A;
 	ocsc_regs.shifts.csc_c12 = mpc20->mpc_shift->MPC_OCSC_C12_A;
@@ -203,6 +236,8 @@ void mpc2_set_ocsc_default(
 			mpc20->base.ctx,
 			regval,
 			&ocsc_regs);
+
+	REG_SET(CSC_MODE[opp_id], 0, MPC_OCSC_MODE, ocsc_mode);
 }
 
 static void mpc2_ogam_get_reg_field(
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h
index 9f53192da2dc..8c77e78e2df5 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mpc.h
@@ -80,6 +80,10 @@
 	SRII(DENORM_CLAMP_G_Y, MPC_OUT, inst),\
 	SRII(DENORM_CLAMP_B_CB, MPC_OUT, inst)
 
+#define MPC_DBG_REG_LIST_DCN2_0() \
+	SR(MPC_OCSC_TEST_DEBUG_DATA),\
+	SR(MPC_OCSC_TEST_DEBUG_INDEX)
+
 #define MPC_REG_VARIABLE_LIST_DCN2_0 \
 	MPC_COMMON_REG_VARIABLE_LIST \
 	uint32_t MPCC_TOP_GAIN[MAX_MPCC]; \
@@ -118,6 +122,8 @@
 	uint32_t MPCC_OGAM_LUT_RAM_CONTROL[MAX_MPCC];\
 	uint32_t MPCC_OGAM_LUT_DATA[MAX_MPCC];\
 	uint32_t MPCC_OGAM_MODE[MAX_MPCC];\
+	uint32_t MPC_OCSC_TEST_DEBUG_DATA;\
+	uint32_t MPC_OCSC_TEST_DEBUG_INDEX;\
 	uint32_t CSC_MODE[MAX_OPP]; \
 	uint32_t CSC_C11_C12_A[MAX_OPP]; \
 	uint32_t CSC_C33_C34_A[MAX_OPP]; \
@@ -134,6 +140,8 @@
 	SF(MPCC0_MPCC_TOP_GAIN, MPCC_TOP_GAIN, mask_sh),\
 	SF(MPCC0_MPCC_BOT_GAIN_INSIDE, MPCC_BOT_GAIN_INSIDE, mask_sh),\
 	SF(MPCC0_MPCC_BOT_GAIN_OUTSIDE, MPCC_BOT_GAIN_OUTSIDE, mask_sh),\
+	SF(MPC_OCSC_TEST_DEBUG_DATA, MPC_OCSC_TEST_DEBUG_DATA, mask_sh),\
+	SF(MPC_OCSC_TEST_DEBUG_INDEX, MPC_OCSC_TEST_DEBUG_INDEX, mask_sh),\
 	SF(MPC_OUT0_CSC_MODE, MPC_OCSC_MODE, mask_sh),\
 	SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C11_A, mask_sh),\
 	SF(MPC_OUT0_CSC_C11_C12_A, MPC_OCSC_C12_A, mask_sh),\
@@ -174,6 +182,12 @@
 	SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MAX_B_CB, mask_sh),\
 	SF(MPC_OUT0_DENORM_CLAMP_B_CB, MPC_OUT_DENORM_CLAMP_MIN_B_CB, mask_sh)
 
+/*
+ *	DCN2 MPC_OCSC debug status register:
+ *
+ *		Field describing current OCSC Mode has index 1 [1..0]
+ */
+#define MPC_OCSC_TEST_DEBUG_DATA_OCSC_MODE_IDX 1
 
 #define MPC_REG_FIELD_LIST_DCN2_0(type) \
 	MPC_REG_FIELD_LIST(type)\
@@ -182,6 +196,8 @@
 	type MPCC_TOP_GAIN;\
 	type MPCC_BOT_GAIN_INSIDE;\
 	type MPCC_BOT_GAIN_OUTSIDE;\
+	type MPC_OCSC_TEST_DEBUG_DATA;\
+	type MPC_OCSC_TEST_DEBUG_INDEX;\
 	type MPC_OCSC_MODE;\
 	type MPC_OCSC_C11_A;\
 	type MPC_OCSC_C12_A;\
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index b715ecc1b5e6..a05746142ec8 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -706,6 +706,7 @@ static const struct dcn20_mpc_registers mpc_regs = {
 		MPC_OUT_MUX_REG_LIST_DCN2_0(3),
 		MPC_OUT_MUX_REG_LIST_DCN2_0(4),
 		MPC_OUT_MUX_REG_LIST_DCN2_0(5),
+		MPC_DBG_REG_LIST_DCN2_0()
 };
 
 static const struct dcn20_mpc_shift mpc_shift = {
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index c76449f58064..5a6e7ac5f785 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -465,7 +465,8 @@ static const struct dcn20_mpc_registers mpc_regs = {
 		MPC_OUT_MUX_REG_LIST_DCN2_0(0),
 		MPC_OUT_MUX_REG_LIST_DCN2_0(1),
 		MPC_OUT_MUX_REG_LIST_DCN2_0(2),
-		MPC_OUT_MUX_REG_LIST_DCN2_0(3)
+		MPC_OUT_MUX_REG_LIST_DCN2_0(3),
+		MPC_DBG_REG_LIST_DCN2_0()
 };
 
 static const struct dcn20_mpc_shift mpc_shift = {
-- 
2.24.1

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  parent reply	other threads:[~2020-01-10 14:47 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-10 14:46 [PATCH 00/43] DC Patches - January 10, 2020 Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 01/43] drm/amd/include: Add OCSC registers Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 02/43] drm/amd/display: Clear state after exiting fixed active VRR state Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 03/43] drm/amd/display: 3.2.65 Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 04/43] drm/amd/display: fix chroma vp wa corner case Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 05/43] drm/amd/display: Fix 300Hz Freesync bug Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 06/43] drm/amd/display: Disable secondary link for certain monitors Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 07/43] drm/amd/display: Adding forgotten hubbub func Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 08/43] drm/amd/display: Flush framebuffer data before passing to DMCUB Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 09/43] drm/amd/display: Read inst_fb data back during DMUB loading Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 10/43] drm/amd/display: Soft reset DMUIF during DMUB reset Rodrigo Siqueira
2020-01-10 14:46 ` Rodrigo Siqueira [this message]
2020-01-10 14:46 ` [PATCH 12/43] drm/amd/display: store lttpr mode with dpcd Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 13/43] drm/amd/display: Don't always set pstate true if dummy latency = 0 Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 14/43] drm/amd/display: Update HDMI hang w/a to apply to all TMDS signals Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 15/43] drm/amd/display: wait for update when setting dpg test pattern Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 16/43] drm/amd/display: stop doing unnecessary detection when going to D3 Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 17/43] drm/amd/display: expand dml structs Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 18/43] drm/amd/display: 3.2.66 Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 19/43] drm/amd/display: Fix double buffering in dcn2 ICSC Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 20/43] drm/amd/display: Driverside changes to support PSR in DMCUB Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 21/43] drm/amd/display: Double buffer dcn2 Gamut Remap Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 22/43] drm/amd/display: programing surface flip by dmcub Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 23/43] drm/amd/display: DMCUB FW Changes to support PSR Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 24/43] drm/amd/display: Indirect reg read macro with shift and mask Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 25/43] drm/amd/display: Refactor surface flip programming Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 26/43] drm/amd/display: Fix DMUB PSR command IDs Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 27/43] drm/amd/display: Add w/a to reset PHY before link training in verify_link_cap Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 28/43] drm/amd/display: rename _lvp to l_vp Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 29/43] drm/amd/display: Use SMU ClockTable Values for DML Calculations Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 30/43] drm/amd/display: Add default switch case for DCC Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 31/43] drm/amd/display: implement fw-driver interface for abm 2.4 Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 32/43] drm/amd/display: remove psr state condition when psr exit case Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 33/43] drm/amd/display: 3.2.67 Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 34/43] drm/amd/display: make PSR static screen entry within 30 ms Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 35/43] drm/amd/display: wait for test pattern after when all pipes are programmed Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 36/43] drm/amd/display: Add monitor patch for AUO dpcd issue Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 37/43] drm/amd/display: Enable double buffer for OTG_BLANK Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 38/43] drm/amd/display: Only program surface flip for video plane via dmcub Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 39/43] drm/amd/display: Use udelay to avoid context switch Rodrigo Siqueira
2020-01-10 15:01   ` Christian König
2020-01-10 18:47     ` Liu, Zhan
2020-01-10 21:16       ` Harry Wentland
2020-01-10 21:30         ` Harry Wentland
2020-01-11 16:34           ` Christian König
2020-01-13 17:12             ` Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 40/43] drm/amd/display: fixup DML dependencies Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 41/43] drm/amd/display: reallocate MST payload when link loss Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 42/43] drm/amd/display: 3.2.68 Rodrigo Siqueira
2020-01-10 14:46 ` [PATCH 43/43] drm/amd/display: skip opp blank or unblank if test pattern enabled Rodrigo Siqueira

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