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From: Andre Przywara <andre.przywara@arm.com>
To: u-boot@lists.denx.de
Subject: [PATCH 12/15] net: sun8i_emac: Simplify and fix error handling for RX
Date: Mon,  6 Jul 2020 01:40:43 +0100	[thread overview]
Message-ID: <20200706004046.20842-13-andre.przywara@arm.com> (raw)
In-Reply-To: <20200706004046.20842-1-andre.przywara@arm.com>

The error handling in recv() is somewhat broken, for instance
good_packet isn't really used, and it's hardly readable. Also we try
to check for short or too big packets, but those are actually filtered
out by the hardware.

Simplify the whole routine and improve the error handling:
- Bail out early if the current RX descriptor is not ready.
- Enable propagation of runt, huge and broken packets.
- Check for runt and huge packets, and return 0 to indicate this.
  This will force the framework to call free_pkt for cleanup.
- Avoid aligning the packet buffer for invalidation again.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
 drivers/net/sun8i_emac.c | 56 +++++++++++++++++++++-------------------
 1 file changed, 30 insertions(+), 26 deletions(-)

diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c
index e2694d3619..48ba244f21 100644
--- a/drivers/net/sun8i_emac.c
+++ b/drivers/net/sun8i_emac.c
@@ -107,6 +107,8 @@
 #define	EMAC_RX_CTL0_RX_EN		BIT(31)
 #define EMAC_RX_CTL1		0x28
 #define	EMAC_RX_CTL1_RX_MD		BIT(1)
+#define	EMAC_RX_CTL1_RX_RUNT_FRM	BIT(2)
+#define	EMAC_RX_CTL1_RX_ERR_FRM		BIT(3)
 #define	EMAC_RX_CTL1_RX_DMA_EN		BIT(30)
 #define	EMAC_RX_CTL1_RX_DMA_START	BIT(31)
 #define EMAC_RX_DMA_DESC	0x34
@@ -125,6 +127,8 @@
 #define EMAC_DESC_FIRST_DESC	BIT(29)
 #define EMAC_DESC_CHAIN_SECOND	BIT(24)
 
+#define EMAC_DESC_RX_ERROR_MASK	0x400068db
+
 DECLARE_GLOBAL_DATA_PTR;
 
 enum emac_variant {
@@ -485,7 +489,8 @@ static int sun8i_emac_eth_start(struct udevice *dev)
 	sun8i_adjust_link(priv, priv->phydev);
 
 	/* Start RX/TX DMA */
-	setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN);
+	setbits_le32(priv->mac_reg + EMAC_RX_CTL1, EMAC_RX_CTL1_RX_DMA_EN |
+		     EMAC_RX_CTL1_RX_ERR_FRM | EMAC_RX_CTL1_RX_RUNT_FRM);
 	setbits_le32(priv->mac_reg + EMAC_TX_CTL1, EMAC_TX_CTL1_TX_DMA_EN);
 
 	/* Enable RX/TX */
@@ -565,10 +570,8 @@ static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 	struct emac_eth_dev *priv = dev_get_priv(dev);
 	u32 status, desc_num = priv->rx_currdescnum;
 	struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
-	int length = -EAGAIN;
-	int good_packet = 1;
-	ulong data_start = (uintptr_t)desc_p->buf_addr;
-	ulong data_end;
+	uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
+	int length;
 
 	/* Invalidate entire buffer descriptor */
 	cache_inv_descriptor(desc_p);
@@ -576,30 +579,31 @@ static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
 	status = desc_p->status;
 
 	/* Check for DMA own bit */
-	if (!(status & EMAC_DESC_OWN_DMA)) {
-		length = (desc_p->status >> 16) & 0x3FFF;
+	if (status & EMAC_DESC_OWN_DMA)
+		return -EAGAIN;
 
-		if (length < 0x40) {
-			good_packet = 0;
-			debug("RX: Bad Packet (runt)\n");
-		}
+	length = (status >> 16) & 0x3fff;
 
-		data_end = data_start + length;
-		/* Invalidate received data */
-		invalidate_dcache_range(rounddown(data_start,
-						  ARCH_DMA_MINALIGN),
-					roundup(data_end,
-						ARCH_DMA_MINALIGN));
-		if (good_packet) {
-			if (length > CONFIG_ETH_RXSIZE) {
-				printf("Received packet is too big (len=%d)\n",
-				       length);
-				return -EMSGSIZE;
-			}
-			*packetp = (uchar *)(ulong)desc_p->buf_addr;
-			return length;
-		}
+	/* make sure we read from DRAM, not our cache */
+	invalidate_dcache_range(data_start,
+				data_start + roundup(length, ARCH_DMA_MINALIGN));
+
+	if (status & EMAC_DESC_RX_ERROR_MASK) {
+		debug("RX: packet error: 0x%x\n",
+		      status & EMAC_DESC_RX_ERROR_MASK);
+		return 0;
 	}
+	if (length < 0x40) {
+		debug("RX: Bad Packet (runt)\n");
+		return 0;
+	}
+
+	if (length > CONFIG_ETH_RXSIZE) {
+		debug("RX: Too large packet (%d bytes)\n", length);
+		return 0;
+	}
+
+	*packetp = (uchar *)(ulong)desc_p->buf_addr;
 
 	return length;
 }
-- 
2.17.5

  parent reply	other threads:[~2020-07-06  0:40 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-06  0:40 [PATCH 00/15] net: sun8i-emac fixes and cleanups Andre Przywara
2020-07-06  0:40 ` [PATCH 01/15] net: sun8i-emac: Bail out on PHY error Andre Przywara
2020-07-06  0:40 ` [PATCH 02/15] net: sun8i_emac: Don't hand out TX descriptor too early Andre Przywara
2020-07-06  0:40 ` [PATCH 03/15] net: sun8i_emac: Simplify mdio_read/mdio_write functions Andre Przywara
2020-07-06  0:40 ` [PATCH 04/15] net: sun8i_emac: Remove pointless wrapper functions Andre Przywara
2020-07-06  0:40 ` [PATCH 05/15] net: sun8i_emac: Name magic bits and simplify read-modify-write calls Andre Przywara
2020-07-06  0:40 ` [PATCH 06/15] net: sun8i_emac: Improve cache maintenance on RX descriptor init Andre Przywara
2020-07-06  0:40 ` [PATCH 07/15] net: sun8i_emac: Reduce cache maintenance on TX " Andre Przywara
2020-07-06  0:40 ` [PATCH 08/15] net: sun8i_emac: Drop unneeded cache invalidation before sending Andre Przywara
2020-07-06  0:40 ` [PATCH 09/15] net: sun8i_emac: Wrap and simplify cache maintenance operations Andre Przywara
2020-07-06  0:40 ` [PATCH 10/15] net: sun8i_emac: Fix overlong lines Andre Przywara
2020-07-06  0:40 ` [PATCH 11/15] net: sun8i_emac: Fix MAC soft reset Andre Przywara
2020-07-06  0:40 ` Andre Przywara [this message]
2020-07-06  0:40 ` [PATCH 13/15] net: sun8i-emac: Make internal PHY handling more robust Andre Przywara
2020-07-06  0:40 ` [PATCH 14/15] net: sun8i-emac: Lower MDIO frequency Andre Przywara
2020-07-11  9:27   ` Jagan Teki
2020-07-11 23:53     ` André Przywara
2020-07-06  0:40 ` [PATCH 15/15] sunxi: Pine-H64: Explicitly enable PHY regulator Andre Przywara
2020-07-06 12:10 ` [PATCH 00/15] net: sun8i-emac fixes and cleanups Maxime Ripard
2020-07-07 13:59 ` Amit Tomer

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