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From: Mark Brown <broonie@kernel.org>
To: Xu Yilun <yilun.xu@intel.com>
Cc: lee.jones@linaro.org, linux-kernel@vger.kernel.org,
	trix@redhat.com, matthew.gerlach@linux.intel.com,
	russell.h.weight@intel.com, lgoncalv@redhat.com,
	hao.wu@intel.com
Subject: Re: [PATCH v2 2/3] regmap: spi-avmm: start with the last SOP on phy rx buffer parsing
Date: Fri, 17 Jul 2020 13:11:05 +0100	[thread overview]
Message-ID: <20200717121105.GE4316@sirena.org.uk> (raw)
In-Reply-To: <1594896174-18826-3-git-send-email-yilun.xu@intel.com>

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On Thu, Jul 16, 2020 at 06:42:53PM +0800, Xu Yilun wrote:
> From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> 
> This patch works around a bug in the SPI Slave to Avalon Master bridge.
> The SPI slave will send an unexpected extra SOP in the following case.

This is fixing a bug introduced in patch 1 - just send a version of
patch 1 that works, don't incrementally fix it.

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  reply	other threads:[~2020-07-17 12:11 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-16 10:42 [PATCH v2 0/3] add regmap-spi-avmm & Intel Max10 BMC chip support Xu Yilun
2020-07-16 10:42 ` [PATCH v2 1/3] regmap: add Intel SPI Slave to AVMM Bus Bridge support Xu Yilun
2020-07-17 18:15   ` Mark Brown
2020-07-20 17:11     ` Xu Yilun
2020-07-22 11:32       ` Mark Brown
2020-07-23  1:30         ` Xu Yilun
2020-07-16 10:42 ` [PATCH v2 2/3] regmap: spi-avmm: start with the last SOP on phy rx buffer parsing Xu Yilun
2020-07-17 12:11   ` Mark Brown [this message]
2020-07-16 10:42 ` [PATCH v2 3/3] mfd: intel-m10-bmc: add Max10 BMC chip support for Intel FPGA PAC Xu Yilun
2020-07-17  9:45   ` Lee Jones
2020-07-21  3:26     ` Xu Yilun
2020-07-17 18:16   ` Mark Brown
2020-07-21  3:47     ` Xu Yilun
2020-07-21  3:50       ` Xu Yilun

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