Hi Greentime,

[FYI, it's a private test report for your RFC patch.]
[auto build test ERROR on linus/master]
[also build test ERROR on v5.9-rc4]
[cannot apply to next-20200910]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/Greentime-Hu/riscv-Add-vector-ISA-support/20200910-163426
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 7fe10096c1508c7f033d34d0741809f8eecc1ed4
config: riscv-allmodconfig (attached as .config)
compiler: riscv64-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=riscv 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

   arch/riscv/kernel/vector.S: Assembler messages:
>> arch/riscv/kernel/vector.S:40: Error: unrecognized opcode `vsetvli t4,x0,e8,m8'
   arch/riscv/kernel/vector.S:41: Error: unrecognized opcode `vse8.v v0,(a1)'
   arch/riscv/kernel/vector.S:43: Error: unrecognized opcode `vse8.v v8,(a1)'
   arch/riscv/kernel/vector.S:45: Error: unrecognized opcode `vse8.v v16,(a1)'
   arch/riscv/kernel/vector.S:47: Error: unrecognized opcode `vse8.v v24,(a1)'
   arch/riscv/kernel/vector.S:62: Error: unrecognized opcode `vsetvli t4,x0,e8,m8'
   arch/riscv/kernel/vector.S:63: Error: unrecognized opcode `vle8.v v0,(a1)'
   arch/riscv/kernel/vector.S:65: Error: unrecognized opcode `vle8.v v8,(a1)'
   arch/riscv/kernel/vector.S:67: Error: unrecognized opcode `vle8.v v16,(a1)'
   arch/riscv/kernel/vector.S:69: Error: unrecognized opcode `vle8.v v24,(a1)'
   arch/riscv/kernel/vector.S:75: Error: unrecognized opcode `vsetvl x0,t2,t1'

# https://github.com/0day-ci/linux/commit/687d8fe1eaec50d49a9f81c3b188cbf023c56850
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Greentime-Hu/riscv-Add-vector-ISA-support/20200910-163426
git checkout 687d8fe1eaec50d49a9f81c3b188cbf023c56850
vim +40 arch/riscv/kernel/vector.S

    31	
    32	ENTRY(__vstate_save)
    33		li      status, SR_VS
    34		csrs    CSR_STATUS, status
    35	
    36		csrr    x_vstart, CSR_VSTART
    37		csrr    x_vtype, CSR_VTYPE
    38		csrr    x_vl, CSR_VL
    39		csrr    x_vcsr, CSR_VCSR
  > 40		vsetvli incr, x0, e8, m8
    41		vse8.v   v0, (datap)
    42		add     datap, datap, incr
    43		vse8.v   v8, (datap)
    44		add     datap, datap, incr
    45		vse8.v   v16, (datap)
    46		add     datap, datap, incr
    47		vse8.v   v24, (datap)
    48	
    49		REG_S   x_vstart, RISCV_V_STATE_VSTART(vstatep)
    50		REG_S   x_vtype, RISCV_V_STATE_VTYPE(vstatep)
    51		REG_S   x_vl, RISCV_V_STATE_VL(vstatep)
    52		REG_S   x_vcsr, RISCV_V_STATE_VCSR(vstatep)
    53	
    54		csrc	CSR_STATUS, status
    55		ret
    56	ENDPROC(__vstate_save)
    57	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org