From: Rob Herring <robh@kernel.org> To: Will Deacon <will@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>, Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>, Arnaldo Carvalho de Melo <acme@kernel.org>, Jiri Olsa <jolsa@redhat.com> Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Alexander Shishkin <alexander.shishkin@linux.intel.com>, Namhyung Kim <namhyung@kernel.org>, Raphael Gault <raphael.gault@arm.com>, Mark Rutland <mark.rutland@arm.com>, Jonathan Cameron <Jonathan.Cameron@huawei.com>, Ian Rogers <irogers@google.com>, honnappa.nagarahalli@arm.com Subject: [PATCH v3 10/10] Documentation: arm64: Document PMU counters access from userspace Date: Fri, 11 Sep 2020 15:51:18 -0600 [thread overview] Message-ID: <20200911215118.2887710-11-robh@kernel.org> (raw) In-Reply-To: <20200911215118.2887710-1-robh@kernel.org> From: Raphael Gault <raphael.gault@arm.com> Add a documentation file to describe the access to the pmu hardware counters from userspace Signed-off-by: Raphael Gault <raphael.gault@arm.com> Signed-off-by: Rob Herring <robh@kernel.org> --- v2: - Update links to test examples Changes from Raphael's v4: - Convert to rSt - Update chained event status - Add section for heterogeneous systems --- Documentation/arm64/index.rst | 1 + .../arm64/perf_counter_user_access.rst | 56 +++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 Documentation/arm64/perf_counter_user_access.rst diff --git a/Documentation/arm64/index.rst b/Documentation/arm64/index.rst index d9665d83c53a..c712a08e7627 100644 --- a/Documentation/arm64/index.rst +++ b/Documentation/arm64/index.rst @@ -15,6 +15,7 @@ ARM64 Architecture legacy_instructions memory perf + perf_counter_user_access pointer-authentication silicon-errata sve diff --git a/Documentation/arm64/perf_counter_user_access.rst b/Documentation/arm64/perf_counter_user_access.rst new file mode 100644 index 000000000000..e49e141f10cc --- /dev/null +++ b/Documentation/arm64/perf_counter_user_access.rst @@ -0,0 +1,56 @@ +============================================= +Access to PMU hardware counter from userspace +============================================= + +Overview +-------- +The perf userspace tool relies on the PMU to monitor events. It offers an +abstraction layer over the hardware counters since the underlying +implementation is cpu-dependent. +Arm64 allows userspace tools to have access to the registers storing the +hardware counters' values directly. + +This targets specifically self-monitoring tasks in order to reduce the overhead +by directly accessing the registers without having to go through the kernel. + +How-to +------ +The focus is set on the armv8 pmuv3 which makes sure that the access to the pmu +registers is enabled and that the userspace has access to the relevant +information in order to use them. + +In order to have access to the hardware counter it is necessary to open the event +using the perf tool interface: the sys_perf_event_open syscall returns a fd which +can subsequently be used with the mmap syscall in order to retrieve a page of +memory containing information about the event. +The PMU driver uses this page to expose to the user the hardware counter's +index and other necessary data. Using this index enables the user to access the +PMU registers using the `mrs` instruction. + +The userspace access is supported in libperf using the perf_evsel__mmap() +and perf_evsel__read() functions. See `tools/lib/perf/tests/test-evsel.c`_ for +an example. + +About heterogeneous systems +--------------------------- +On heterogeneous systems such as big.LITTLE, userspace PMU counter access can +only be enabled when the tasks are pinned to a homogeneous subset of cores and +the corresponding PMU instance is opened by specifying the 'type' attribute. +The use of generic event types is not supported in this case. + +Have a look at `tools/perf/arch/arm64/tests/user-events.c`_ for an example. It +can be run using the perf tool to check that the access to the registers works +correctly from userspace: + +.. code-block:: sh + + perf test -v user + +About chained events +-------------------- +Chained events are not supported in userspace. If a 64-bit counter is requested, +userspace access will only be enabled if the underlying counter is 64-bit. + +.. Links +.. _tools/perf/arch/arm64/tests/user-events.c: + https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/tools/perf/arch/arm64/tests/user-events.c -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: Rob Herring <robh@kernel.org> To: Will Deacon <will@kernel.org>, Catalin Marinas <catalin.marinas@arm.com>, Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@redhat.com>, Arnaldo Carvalho de Melo <acme@kernel.org>, Jiri Olsa <jolsa@redhat.com> Cc: Mark Rutland <mark.rutland@arm.com>, Ian Rogers <irogers@google.com>, Alexander Shishkin <alexander.shishkin@linux.intel.com>, linux-kernel@vger.kernel.org, honnappa.nagarahalli@arm.com, Raphael Gault <raphael.gault@arm.com>, Jonathan Cameron <Jonathan.Cameron@huawei.com>, Namhyung Kim <namhyung@kernel.org>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 10/10] Documentation: arm64: Document PMU counters access from userspace Date: Fri, 11 Sep 2020 15:51:18 -0600 [thread overview] Message-ID: <20200911215118.2887710-11-robh@kernel.org> (raw) In-Reply-To: <20200911215118.2887710-1-robh@kernel.org> From: Raphael Gault <raphael.gault@arm.com> Add a documentation file to describe the access to the pmu hardware counters from userspace Signed-off-by: Raphael Gault <raphael.gault@arm.com> Signed-off-by: Rob Herring <robh@kernel.org> --- v2: - Update links to test examples Changes from Raphael's v4: - Convert to rSt - Update chained event status - Add section for heterogeneous systems --- Documentation/arm64/index.rst | 1 + .../arm64/perf_counter_user_access.rst | 56 +++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 Documentation/arm64/perf_counter_user_access.rst diff --git a/Documentation/arm64/index.rst b/Documentation/arm64/index.rst index d9665d83c53a..c712a08e7627 100644 --- a/Documentation/arm64/index.rst +++ b/Documentation/arm64/index.rst @@ -15,6 +15,7 @@ ARM64 Architecture legacy_instructions memory perf + perf_counter_user_access pointer-authentication silicon-errata sve diff --git a/Documentation/arm64/perf_counter_user_access.rst b/Documentation/arm64/perf_counter_user_access.rst new file mode 100644 index 000000000000..e49e141f10cc --- /dev/null +++ b/Documentation/arm64/perf_counter_user_access.rst @@ -0,0 +1,56 @@ +============================================= +Access to PMU hardware counter from userspace +============================================= + +Overview +-------- +The perf userspace tool relies on the PMU to monitor events. It offers an +abstraction layer over the hardware counters since the underlying +implementation is cpu-dependent. +Arm64 allows userspace tools to have access to the registers storing the +hardware counters' values directly. + +This targets specifically self-monitoring tasks in order to reduce the overhead +by directly accessing the registers without having to go through the kernel. + +How-to +------ +The focus is set on the armv8 pmuv3 which makes sure that the access to the pmu +registers is enabled and that the userspace has access to the relevant +information in order to use them. + +In order to have access to the hardware counter it is necessary to open the event +using the perf tool interface: the sys_perf_event_open syscall returns a fd which +can subsequently be used with the mmap syscall in order to retrieve a page of +memory containing information about the event. +The PMU driver uses this page to expose to the user the hardware counter's +index and other necessary data. Using this index enables the user to access the +PMU registers using the `mrs` instruction. + +The userspace access is supported in libperf using the perf_evsel__mmap() +and perf_evsel__read() functions. See `tools/lib/perf/tests/test-evsel.c`_ for +an example. + +About heterogeneous systems +--------------------------- +On heterogeneous systems such as big.LITTLE, userspace PMU counter access can +only be enabled when the tasks are pinned to a homogeneous subset of cores and +the corresponding PMU instance is opened by specifying the 'type' attribute. +The use of generic event types is not supported in this case. + +Have a look at `tools/perf/arch/arm64/tests/user-events.c`_ for an example. It +can be run using the perf tool to check that the access to the registers works +correctly from userspace: + +.. code-block:: sh + + perf test -v user + +About chained events +-------------------- +Chained events are not supported in userspace. If a 64-bit counter is requested, +userspace access will only be enabled if the underlying counter is 64-bit. + +.. Links +.. _tools/perf/arch/arm64/tests/user-events.c: + https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/tools/perf/arch/arm64/tests/user-events.c -- 2.25.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-09-11 21:52 UTC|newest] Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-09-11 21:51 [PATCH v3 0/10] libperf and arm64 userspace counter access support Rob Herring 2020-09-11 21:51 ` Rob Herring 2020-09-11 21:51 ` [PATCH v3 01/10] arm64: pmu: Add hook to handle pmu-related undefined instructions Rob Herring 2020-09-11 21:51 ` Rob Herring 2020-09-28 18:26 ` Will Deacon 2020-09-28 18:26 ` Will Deacon 2020-09-29 13:46 ` Rob Herring 2020-09-29 13:46 ` Rob Herring 2020-09-29 17:49 ` Will Deacon 2020-09-29 17:49 ` Will Deacon 2020-09-29 20:46 ` Rob Herring 2020-09-29 20:46 ` Rob Herring 2020-09-11 21:51 ` [PATCH v3 02/10] arm64: pmu: Add function implementation to update event index in userpage Rob Herring 2020-09-11 21:51 ` Rob Herring 2020-09-11 21:51 ` [PATCH v3 03/10] arm64: perf: Enable pmu counter direct access for perf event on armv8 Rob Herring 2020-09-11 21:51 ` Rob Herring 2020-09-11 21:51 ` [PATCH v3 04/10] tools/include: Add an initial math64.h Rob Herring 2020-09-11 21:51 ` Rob Herring 2020-09-11 21:51 ` [PATCH v3 05/10] libperf: Add libperf_evsel__mmap() Rob Herring 2020-09-11 21:51 ` Rob Herring 2020-09-18 14:33 ` Jiri Olsa 2020-09-18 14:33 ` Jiri Olsa 2020-09-22 15:28 ` Rob Herring 2020-09-22 15:28 ` Rob Herring 2020-09-22 18:32 ` Jiri Olsa 2020-09-22 18:32 ` Jiri Olsa 2020-09-11 21:51 ` [PATCH v3 06/10] libperf: tests: Add support for verbose printing Rob Herring 2020-09-11 21:51 ` Rob Herring 2020-09-11 21:51 ` [PATCH v3 07/10] libperf: Add support for user space counter access Rob Herring 2020-09-11 21:51 ` Rob Herring 2020-09-11 21:51 ` [PATCH v3 08/10] libperf: Add arm64 support to perf_mmap__read_self() Rob Herring 2020-09-11 21:51 ` Rob Herring 2020-09-11 21:51 ` [PATCH v3 09/10] perf: arm64: Add test for userspace counter access on heterogeneous systems Rob Herring 2020-09-11 21:51 ` Rob Herring 2020-09-11 21:51 ` Rob Herring [this message] 2020-09-11 21:51 ` [PATCH v3 10/10] Documentation: arm64: Document PMU counters access from userspace Rob Herring 2020-09-12 20:53 ` [PATCH v3 0/10] libperf and arm64 userspace counter access support Jiri Olsa 2020-09-12 20:53 ` Jiri Olsa 2020-09-14 14:21 ` Rob Herring 2020-09-14 14:21 ` Rob Herring [not found] ` <CANW9uytmafiNb_8oua9QY7L9O5BQTBFQBOMS3ZgjQ7aWj8CD2Q@mail.gmail.com> 2020-09-16 2:50 ` Rob Herring 2020-09-16 2:50 ` Rob Herring 2020-09-19 7:22 ` Itaru Kitayama 2020-09-19 7:22 ` Itaru Kitayama 2020-09-22 15:23 ` Rob Herring 2020-09-22 15:23 ` Rob Herring
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