From mboxrd@z Thu Jan 1 00:00:00 1970 From: Siew Chin Lim Date: Thu, 1 Oct 2020 02:16:07 -0700 Subject: [v2, 09/16] mmc: dwmmc: socfpga: Add ATF support for MMC driver In-Reply-To: <20201001091614.184612-1-elly.siew.chin.lim@intel.com> References: <20201001091614.184612-1-elly.siew.chin.lim@intel.com> Message-ID: <20201001091614.184612-10-elly.siew.chin.lim@intel.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From: Chee Hong Ang In non-secure mode (EL2), MMC driver calls the SMC/PSCI services provided by ATF to set SDMMC's DRVSEL and SMPLSEL. Signed-off-by: Chee Hong Ang Signed-off-by: Siew Chin Lim --- v2: - Code clean up without functionality change: - Changed socfpga_dwmci_fw_clksel() to socfpga_dwmci_do_clksel(). This function will be called in both legacy and ATF boot flow. - Move #ifdef .. #endif switch into socfpga_dwmci_do_clksel(). - Remove #ifdef .. #endif switch from socfpga_dwmci_clksel(), Directly call socfpga_dwmci_do_clksel() in socfpga_dwmci_clksel(). --- drivers/mmc/socfpga_dw_mmc.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index 0022f943bd..404dd2c91a 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -13,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -46,6 +48,26 @@ static void socfpga_dwmci_reset(struct udevice *dev) reset_deassert_bulk(&reset_bulk); } +static void socfpga_dwmci_do_clksel(u32 sdmmc_mask) +{ +#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF) + u64 args[2]; + + /* drvsel */ + args[0] = (sdmmc_mask >> SYSMGR_SDMMC_DRVSEL_SHIFT) & 0x7; + /* smplsel */ + args[1] = (sdmmc_mask >> SYSMGR_SDMMC_SMPLSEL_SHIFT) & 0x7; + if (invoke_smc(INTEL_SIP_SMC_HPS_SET_SDMMC_CCLK, args, 2, NULL, 0)) + dev_err(host->dev, "SMC call failed in %s\n", __func__); + +#else + writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC); + + debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, + readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC)); +#endif +} + static void socfpga_dwmci_clksel(struct dwmci_host *host) { struct dwmci_socfpga_priv_data *priv = host->priv; @@ -58,10 +80,8 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) debug("%s: drvsel %d smplsel %d\n", __func__, priv->drvsel, priv->smplsel); - writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC); - debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__, - readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC)); + socfpga_dwmci_do_clksel(sdmmc_mask); /* Enable SDMMC clock */ setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN, -- 2.13.0