Hi AKASHI,

[FYI, it's a private test report for your RFC patch.]
[auto build test WARNING on linus/master]
[also build test WARNING on v5.10-rc2]
[cannot apply to v3.1 ulf.hansson-mmc/next mmc/mmc-next next-20201105]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/AKASHI-Takahiro/Add-support-UHS-II-for-GL9755/20201106-103058
base:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 521b619acdc8f1f5acdac15b84f81fd9515b2aff
config: microblaze-randconfig-r005-20201105 (attached as .config)
compiler: microblaze-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/141b3e8afac92e2891a4f66b6428f36233791342
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review AKASHI-Takahiro/Add-support-UHS-II-for-GL9755/20201106-103058
        git checkout 141b3e8afac92e2891a4f66b6428f36233791342
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=microblaze 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/mmc/host/sdhci-pci-gli.c: In function 'sdhci_gl9755_reset':
>> drivers/mmc/host/sdhci-pci-gli.c:776:6: warning: variable 'clk_ctrl' set but not used [-Wunused-but-set-variable]
     776 |  u16 clk_ctrl;
         |      ^~~~~~~~

vim +/clk_ctrl +776 drivers/mmc/host/sdhci-pci-gli.c

   771	
   772	static void sdhci_gl9755_reset(struct sdhci_host *host, u8 mask)
   773	{
   774		ktime_t timeout;
   775		u16 ctrl2;
 > 776		u16 clk_ctrl;
   777	
   778		/* need internal clock */
   779		if (mask & SDHCI_RESET_ALL) {
   780			ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
   781			clk_ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
   782	
   783			if ((ctrl2 & SDHCI_CTRL_V4_MODE) &&
   784			    (ctrl2 & SDHCI_CTRL_UHS2_INTERFACE_EN)) {
   785				sdhci_writew(host,
   786					     SDHCI_CLOCK_INT_EN,
   787					     SDHCI_CLOCK_CONTROL);
   788			} else {
   789				sdhci_writew(host,
   790					     SDHCI_CLOCK_INT_EN,
   791					     SDHCI_CLOCK_CONTROL);
   792				sdhci_wait_clock_stable(host);
   793				sdhci_writew(host,
   794					     SDHCI_CTRL_V4_MODE,
   795					     SDHCI_HOST_CONTROL2);
   796			}
   797		}
   798	
   799		sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
   800	
   801		/* reset sd-tran on UHS2 mode if need to reset cmd/data */
   802		if ((mask & SDHCI_RESET_CMD) | (mask & SDHCI_RESET_DATA))
   803			gl9755_uhs2_reset_sd_tran(host);
   804	
   805		if (mask & SDHCI_RESET_ALL)
   806			host->clock = 0;
   807	
   808		/* Wait max 100 ms */
   809		timeout = ktime_add_ms(ktime_get(), 100);
   810	
   811		/* hw clears the bit when it's done */
   812		while (1) {
   813			bool timedout = ktime_after(ktime_get(), timeout);
   814	
   815			if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask))
   816				break;
   817			if (timedout) {
   818				pr_err("%s: Reset 0x%x never completed.\n",
   819				       mmc_hostname(host->mmc), (int)mask);
   820				sdhci_dumpregs(host);
   821				/* manual clear */
   822				sdhci_writeb(host, 0, SDHCI_SOFTWARE_RESET);
   823				return;
   824			}
   825			udelay(10);
   826		}
   827	}
   828	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org