All of lore.kernel.org
 help / color / mirror / Atom feed
From: Siew Chin Lim <elly.siew.chin.lim@intel.com>
To: u-boot@lists.denx.de
Subject: [RESEND v2 09/22] arm: socfpga: Add handoff data support for Diamond Mesa
Date: Mon,  9 Nov 2020 22:44:26 -0800	[thread overview]
Message-ID: <20201110064439.9683-10-elly.siew.chin.lim@intel.com> (raw)
In-Reply-To: <20201110064439.9683-1-elly.siew.chin.lim@intel.com>

Diamond Mesa support both HPS handoff data and DDR handoff data.
HPS handoff data support re-use Straix10 and Agilex code. DDR
handoff data is newly introduced in Diamond Mesa.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
---
 arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 19 ++++++++++
 arch/arm/mach-socfpga/wrap_handoff_soc64.c         | 40 ++++++++++++++++++++++
 2 files changed, 59 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index 68e0278384..c38b232065 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -23,8 +23,27 @@
 #define SOC64_HANDOFF_OFFSET_DATA		0x10
 #define SOC64_HANDOFF_SIZE			4096
 
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+	defined(CONFIG_TARGET_SOCFPGA_AGILEX)
 #define SOC64_HANDOFF_BASE			0xFFE3F000
 #define SOC64_HANDOFF_MISC			(SOC64_HANDOFF_BASE + 0x610)
+#elif defined(CONFIG_TARGET_SOCFPGA_DM)
+#define SOC64_HANDOFF_BASE			0xFFE5F000
+#define SOC64_HANDOFF_MISC			(SOC64_HANDOFF_BASE + 0x630)
+
+/* DDR handoff */
+#define SOC64_HANDOFF_DDR_BASE			0xFFE5C000
+
+#define SOC64_HANDOFF_DDR_MAGIC			0x48524444
+#define SOC64_HANDOFF_DDR_UMCTL2_MAGIC		0x4C54434D
+#define SOC64_HANDOFF_DDR_MEMRESET_BASE		(SOC64_HANDOFF_DDR_BASE + 0xC)
+#define SOC64_HANDOFF_DDR_UMCTL2_SECTION	(SOC64_HANDOFF_DDR_BASE + 0x10)
+#define SOC64_HANDOFF_DDR_UMCTL2_BASE		(SOC64_HANDOFF_DDR_BASE + 0x1C)
+#define SOC64_HANDOFF_DDR_PHY_MAGIC		0x43594850
+#define SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC	0x45594850
+#define SOC64_HANDOFF_DDR_PHY_BASE_OFFSET	0x8
+#endif
+
 #define SOC64_HANDOFF_MUX			(SOC64_HANDOFF_BASE + 0x10)
 #define SOC64_HANDOFF_IOCTL			(SOC64_HANDOFF_BASE + 0x1A0)
 #define SOC64_HANDOFF_FPGA			(SOC64_HANDOFF_BASE + 0x330)
diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
index 672bdd5230..aea384897e 100644
--- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
+++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
@@ -67,6 +67,46 @@ int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len,
 			debug("at addr  0x%p\n", (u32 *)handoff_address);
 			return -EPERM;
 		}
+	} else {
+#ifdef CONFIG_TARGET_SOCFPGA_DM
+		temp = readl(handoff_address);
+		if (temp == SOC64_HANDOFF_DDR_UMCTL2_MAGIC) {
+			debug("%s: umctl2 handoff data =\n{\n",
+			      __func__);
+		} else if (temp == SOC64_HANDOFF_DDR_PHY_MAGIC) {
+			debug("%s: PHY handoff data =\n{\n",
+			      __func__);
+		} else if (temp == SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC) {
+			debug("%s: PHY engine handoff data =\n{\n",
+			      __func__);
+		}
+
+		debug("handoff table address = 0x%p table length = 0x%x\n",
+		      table_x32, table_len);
+
+		if (temp == SOC64_HANDOFF_DDR_UMCTL2_MAGIC ||
+		    temp == SOC64_HANDOFF_DDR_PHY_MAGIC ||
+		    temp == SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC) {
+			/* Using handoff from Quartus tools if exists */
+			for (i = 0; i < table_len; i++) {
+				*table_x32 = readl(handoff_address +
+						SOC64_HANDOFF_OFFSET_DATA + (i * 4));
+
+				if (!(i % 2))
+					debug(" No.%d Addr 0x%08x: ", i,
+					      *table_x32);
+				else
+					debug(" 0x%08x\n", *table_x32);
+
+				table_x32++;
+			}
+			debug("\n}\n");
+		} else {
+			debug("%s: Cannot find HANDOFF MAGIC ", __func__);
+			debug("at addr 0x%p\n", (u32 *)handoff_address);
+			return -EPERM;
+		}
+#endif
 	}
 
 	return 0;
-- 
2.13.0

  parent reply	other threads:[~2020-11-10  6:44 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-10  6:44 [RESEND v2 00/22] Add Intel Diamond Mesa SoC support Siew Chin Lim
2020-11-10  6:44 ` [RESEND v2 01/22] arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64 Siew Chin Lim
2020-11-13  3:41   ` Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 02/22] arm: socfpga: dm: Add base address for Intel Diamond Mesa Siew Chin Lim
2020-11-13  3:43   ` Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 03/22] arm: socfpga: dm: Add firewall support for Agilex and " Siew Chin Lim
2020-11-13  3:48   ` Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 04/22] arm: socfpga: Rename Stratix10 and Agilex handoff common macros Siew Chin Lim
2020-11-13  3:51   ` Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 05/22] arm: socfpga: Changed wrap_pll_config_s10.c to wrap_pll_config_soc64.c Siew Chin Lim
2020-11-13  3:52   ` Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 06/22] arm: socfpga: Changed system_manager_s10.c to system_manager_soc64.c Siew Chin Lim
2020-11-13  3:54   ` Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 07/22] arm: socfpga: Rearrange sequence of macros in handoff_soc64.h Siew Chin Lim
2020-11-13  3:57   ` Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 08/22] arm: socfpga: Restructure Stratix10 and Agilex handoff code Siew Chin Lim
2020-11-19 10:16   ` Tan, Ley Foon
2020-11-10  6:44 ` Siew Chin Lim [this message]
2020-11-19 10:39   ` [RESEND v2 09/22] arm: socfpga: Add handoff data support for Diamond Mesa Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 10/22] drivers: clk: dm: Add clock driver " Siew Chin Lim
2020-11-20  9:24   ` Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 11/22] arm: socfpga: dm: Get clock manager base address " Siew Chin Lim
2020-11-10  6:44 ` [RESEND v2 12/22] drivers: clk: dm: Add memory clock driver " Siew Chin Lim
2020-11-23  7:53   ` Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 13/22] arm: socfpga: Move Stratix10 and Agilex clock manager common code Siew Chin Lim
2020-11-23  7:58   ` Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 14/22] arm: socfpga: Changed to store QSPI reference clock in kHz Siew Chin Lim
2020-11-23  8:38   ` Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 15/22] arm: socfpga: dm: Add clock manager for Diamond Mesa Siew Chin Lim
2020-11-23  8:45   ` Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 16/22] ddr: altera: dm: Add SDRAM driver " Siew Chin Lim
2020-11-23 10:37   ` Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 17/22] arm: socfpga: Move Stratix10 and Agilex SPL common code Siew Chin Lim
2020-11-23 10:38   ` Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 18/22] arm: socfpga: dm: Add SPL for Diamond Mesa Siew Chin Lim
2020-11-23 10:40   ` Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 19/22] board: intel: dm: Add socdk board support " Siew Chin Lim
2020-11-23 10:41   ` Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 20/22] arm: dts: dm: Add base dtsi and devkit dts " Siew Chin Lim
2020-11-23 10:53   ` Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 21/22] configs: dm: Add Diamond Mesa CONFIGs Siew Chin Lim
2020-11-23 10:55   ` Tan, Ley Foon
2020-11-10  6:44 ` [RESEND v2 22/22] arm: socfpga: dm: Enable Intel Diamond Mesa build Siew Chin Lim
2020-11-23 10:57   ` Tan, Ley Foon

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20201110064439.9683-10-elly.siew.chin.lim@intel.com \
    --to=elly.siew.chin.lim@intel.com \
    --cc=u-boot@lists.denx.de \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.