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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id y10sm1618407pjm.34.2020.11.18.00.33.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Nov 2020 00:33:12 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC 14/15] target/riscv: rvb: add/sub with postfix zero-extend Date: Wed, 18 Nov 2020 16:29:52 +0800 Message-Id: <20201118083044.13992-15-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201118083044.13992-1-frank.chang@sifive.com> References: <20201118083044.13992-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x102e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Alistair Francis , Palmer Dabbelt , Kito Cheng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Kito Cheng Signed-off-by: Kito Cheng --- target/riscv/insn32-64.decode | 7 +++++ target/riscv/insn_trans/trans_rvb.c.inc | 38 +++++++++++++++++++++++++ target/riscv/translate.c | 18 ++++++++++++ 3 files changed, 63 insertions(+) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 42bafbc03a0..5df10cd3066 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -107,6 +107,9 @@ gorcw 0010100 .......... 101 ..... 0111011 @r sh1addu_w 0010000 .......... 010 ..... 0111011 @r sh2addu_w 0010000 .......... 100 ..... 0111011 @r sh3addu_w 0010000 .......... 110 ..... 0111011 @r +addwu 0000101 .......... 000 ..... 0111011 @r +subwu 0100101 .......... 000 ..... 0111011 @r +addu_w 0000100 .......... 000 ..... 0111011 @r sbsetiw 0010100 .......... 001 ..... 0011011 @sh5 sbclriw 0100100 .......... 001 ..... 0011011 @sh5 @@ -116,3 +119,7 @@ sroiw 0010000 .......... 101 ..... 0011011 @sh5 roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 + +addiwu ................. 100 ..... 0011011 @i + +slliu_w 000010 ........... 001 ..... 0011011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 31d791236d9..c6fcdc5f0c1 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -434,4 +434,42 @@ GEN_TRANS_SHADDU_W(1) GEN_TRANS_SHADDU_W(2) GEN_TRANS_SHADDU_W(3) +static bool trans_addwu(DisasContext *ctx, arg_addwu *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_addwu); +} + +static bool trans_addiwu(DisasContext *ctx, arg_addiwu *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith_imm_tl(ctx, a, &gen_addwu); +} + +static bool trans_subwu(DisasContext *ctx, arg_subwu *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_subwu); +} + +static bool trans_addu_w(DisasContext *ctx, arg_addu_w *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_addu_w); +} + +static bool trans_slliu_w(DisasContext *ctx, arg_slliu_w *a) +{ + TCGv source1; + source1 = tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + + tcg_gen_ext32u_tl(source1, source1); + tcg_gen_shli_tl(source1, source1, a->shamt); + gen_set_gpr(a->rd, source1); + + tcg_temp_free(source1); + return true; +} + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 584550a9db2..9d36d2bd685 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -672,12 +672,24 @@ static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) tcg_gen_ext32s_tl(ret, ret); } +static void gen_addwu(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_add_tl(ret, arg1, arg2); + tcg_gen_ext32u_tl(ret, ret); +} + static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2) { tcg_gen_sub_tl(ret, arg1, arg2); tcg_gen_ext32s_tl(ret, ret); } +static void gen_subwu(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_sub_tl(ret, arg1, arg2); + tcg_gen_ext32u_tl(ret, ret); +} + static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2) { tcg_gen_mul_tl(ret, arg1, arg2); @@ -1252,6 +1264,12 @@ GEN_SHADDU_W(1) GEN_SHADDU_W(2) GEN_SHADDU_W(3) +static void gen_addu_w(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_ext32u_tl(arg1, arg1); + tcg_gen_add_tl(ret, arg1, arg2); +} + #endif static bool gen_arith(DisasContext *ctx, arg_r *a, -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kfIu0-0002jj-0M for mharc-qemu-riscv@gnu.org; Wed, 18 Nov 2020 03:33:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50872) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfItx-0002hO-Fk for qemu-riscv@nongnu.org; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id y10sm1618407pjm.34.2020.11.18.00.33.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Nov 2020 00:33:12 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Kito Cheng , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , Frank Chang Subject: [RFC 14/15] target/riscv: rvb: add/sub with postfix zero-extend Date: Wed, 18 Nov 2020 16:29:52 +0800 Message-Id: <20201118083044.13992-15-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201118083044.13992-1-frank.chang@sifive.com> References: <20201118083044.13992-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1031.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Nov 2020 08:33:18 -0000 From: Kito Cheng Signed-off-by: Kito Cheng --- target/riscv/insn32-64.decode | 7 +++++ target/riscv/insn_trans/trans_rvb.c.inc | 38 +++++++++++++++++++++++++ target/riscv/translate.c | 18 ++++++++++++ 3 files changed, 63 insertions(+) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 42bafbc03a0..5df10cd3066 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -107,6 +107,9 @@ gorcw 0010100 .......... 101 ..... 0111011 @r sh1addu_w 0010000 .......... 010 ..... 0111011 @r sh2addu_w 0010000 .......... 100 ..... 0111011 @r sh3addu_w 0010000 .......... 110 ..... 0111011 @r +addwu 0000101 .......... 000 ..... 0111011 @r +subwu 0100101 .......... 000 ..... 0111011 @r +addu_w 0000100 .......... 000 ..... 0111011 @r sbsetiw 0010100 .......... 001 ..... 0011011 @sh5 sbclriw 0100100 .......... 001 ..... 0011011 @sh5 @@ -116,3 +119,7 @@ sroiw 0010000 .......... 101 ..... 0011011 @sh5 roriw 0110000 .......... 101 ..... 0011011 @sh5 greviw 0110100 .......... 101 ..... 0011011 @sh5 gorciw 0010100 .......... 101 ..... 0011011 @sh5 + +addiwu ................. 100 ..... 0011011 @i + +slliu_w 000010 ........... 001 ..... 0011011 @sh diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 31d791236d9..c6fcdc5f0c1 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -434,4 +434,42 @@ GEN_TRANS_SHADDU_W(1) GEN_TRANS_SHADDU_W(2) GEN_TRANS_SHADDU_W(3) +static bool trans_addwu(DisasContext *ctx, arg_addwu *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_addwu); +} + +static bool trans_addiwu(DisasContext *ctx, arg_addiwu *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith_imm_tl(ctx, a, &gen_addwu); +} + +static bool trans_subwu(DisasContext *ctx, arg_subwu *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_subwu); +} + +static bool trans_addu_w(DisasContext *ctx, arg_addu_w *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_arith(ctx, a, &gen_addu_w); +} + +static bool trans_slliu_w(DisasContext *ctx, arg_slliu_w *a) +{ + TCGv source1; + source1 = tcg_temp_new(); + gen_get_gpr(source1, a->rs1); + + tcg_gen_ext32u_tl(source1, source1); + tcg_gen_shli_tl(source1, source1, a->shamt); + gen_set_gpr(a->rd, source1); + + tcg_temp_free(source1); + return true; +} + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 584550a9db2..9d36d2bd685 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -672,12 +672,24 @@ static void gen_addw(TCGv ret, TCGv arg1, TCGv arg2) tcg_gen_ext32s_tl(ret, ret); } +static void gen_addwu(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_add_tl(ret, arg1, arg2); + tcg_gen_ext32u_tl(ret, ret); +} + static void gen_subw(TCGv ret, TCGv arg1, TCGv arg2) { tcg_gen_sub_tl(ret, arg1, arg2); tcg_gen_ext32s_tl(ret, ret); } +static void gen_subwu(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_sub_tl(ret, arg1, arg2); + tcg_gen_ext32u_tl(ret, ret); +} + static void gen_mulw(TCGv ret, TCGv arg1, TCGv arg2) { tcg_gen_mul_tl(ret, arg1, arg2); @@ -1252,6 +1264,12 @@ GEN_SHADDU_W(1) GEN_SHADDU_W(2) GEN_SHADDU_W(3) +static void gen_addu_w(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_ext32u_tl(arg1, arg1); + tcg_gen_add_tl(ret, arg1, arg2); +} + #endif static bool gen_arith(DisasContext *ctx, arg_r *a, -- 2.17.1