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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id y10sm1618407pjm.34.2020.11.18.00.32.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Nov 2020 00:32:22 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC 03/15] target/riscv: rvb: count bits set Date: Wed, 18 Nov 2020 16:29:41 +0800 Message-Id: <20201118083044.13992-4-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201118083044.13992-1-frank.chang@sifive.com> References: <20201118083044.13992-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1033.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Sagar Karandikar , Frank Chang , Bastian Koppelmann , Alistair Francis , Palmer Dabbelt , Kito Cheng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Kito Cheng Signed-off-by: Kito Cheng --- target/riscv/insn32-64.decode | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++ target/riscv/translate.c | 21 +++++++++++++++++++++ 4 files changed, 35 insertions(+) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 250279e62ea..d5bea5af273 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -90,3 +90,4 @@ hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s # *** RV64B Standard Extension (in addition to RV32B) *** clzw 011000000000 ..... 001 ..... 0011011 @r2 ctzw 011000000001 ..... 001 ..... 0011011 @r2 +pcntw 011000000010 ..... 001 ..... 0011011 @r2 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 884ed2a42fa..9e70a85d6f0 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -597,3 +597,4 @@ vsetvl 1000000 ..... ..... 111 ..... 1010111 @r # *** RV32B Standard Extension *** clz 011000000000 ..... 001 ..... 0010011 @r2 ctz 011000000001 ..... 001 ..... 0010011 @r2 +pcnt 011000000010 ..... 001 ..... 0010011 @r2 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 1f02cb91a0a..6f1054e3908 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -29,6 +29,12 @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a) return gen_cxz(ctx, a, &tcg_gen_ctzi_tl); } +static bool trans_pcnt(DisasContext *ctx, arg_pcnt *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_unary(ctx, a, &tcg_gen_ctpop_tl); +} + /* RV64-only instructions */ #ifdef TARGET_RISCV64 @@ -44,4 +50,10 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) return gen_cxzw(ctx, a, &tcg_gen_ctzi_i32); } +static bool trans_pcntw(DisasContext *ctx, arg_pcntw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_unary(ctx, a, &gen_pcntw); +} + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 20b47f7a660..97e5899750e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -736,6 +736,12 @@ static bool gen_cxzw(DisasContext *ctx, arg_r2 *a, return true; } +static void gen_pcntw(TCGv ret, TCGv arg1) +{ + tcg_gen_ext32u_tl(arg1, arg1); + tcg_gen_ctpop_tl(ret, arg1); +} + #endif static bool gen_arith(DisasContext *ctx, arg_r *a, @@ -793,6 +799,21 @@ static bool gen_cxz(DisasContext *ctx, arg_r2 *a, return true; } +static bool gen_unary(DisasContext *ctx, arg_r2 *a, + void(*func)(TCGv, TCGv)) +{ + TCGv source; + source = tcg_temp_new(); + + gen_get_gpr(source, a->rs1); + + (*func)(source, source); + + gen_set_gpr(a->rd, source); + tcg_temp_free(source); + return true; +} + /* Include insn module translation function */ #include "insn_trans/trans_rvi.c.inc" #include "insn_trans/trans_rvm.c.inc" -- 2.17.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1kfIt9-0000qf-R5 for mharc-qemu-riscv@gnu.org; Wed, 18 Nov 2020 03:32:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50402) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kfIt7-0000lJ-Ts for qemu-riscv@nongnu.org; Wed, 18 Nov 2020 03:32:25 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:35765) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kfIt5-0004mS-Nb for qemu-riscv@nongnu.org; Wed, 18 Nov 2020 03:32:25 -0500 Received: by mail-pj1-x1029.google.com with SMTP id b12so717552pjl.0 for ; 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[114.34.229.221]) by smtp.gmail.com with ESMTPSA id y10sm1618407pjm.34.2020.11.18.00.32.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Nov 2020 00:32:22 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Kito Cheng , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Bastian Koppelmann , Frank Chang Subject: [RFC 03/15] target/riscv: rvb: count bits set Date: Wed, 18 Nov 2020 16:29:41 +0800 Message-Id: <20201118083044.13992-4-frank.chang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201118083044.13992-1-frank.chang@sifive.com> References: <20201118083044.13992-1-frank.chang@sifive.com> Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=frank.chang@sifive.com; helo=mail-pj1-x1029.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Nov 2020 08:32:26 -0000 From: Kito Cheng Signed-off-by: Kito Cheng --- target/riscv/insn32-64.decode | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvb.c.inc | 12 ++++++++++++ target/riscv/translate.c | 21 +++++++++++++++++++++ 4 files changed, 35 insertions(+) diff --git a/target/riscv/insn32-64.decode b/target/riscv/insn32-64.decode index 250279e62ea..d5bea5af273 100644 --- a/target/riscv/insn32-64.decode +++ b/target/riscv/insn32-64.decode @@ -90,3 +90,4 @@ hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s # *** RV64B Standard Extension (in addition to RV32B) *** clzw 011000000000 ..... 001 ..... 0011011 @r2 ctzw 011000000001 ..... 001 ..... 0011011 @r2 +pcntw 011000000010 ..... 001 ..... 0011011 @r2 diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 884ed2a42fa..9e70a85d6f0 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -597,3 +597,4 @@ vsetvl 1000000 ..... ..... 111 ..... 1010111 @r # *** RV32B Standard Extension *** clz 011000000000 ..... 001 ..... 0010011 @r2 ctz 011000000001 ..... 001 ..... 0010011 @r2 +pcnt 011000000010 ..... 001 ..... 0010011 @r2 diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index 1f02cb91a0a..6f1054e3908 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -29,6 +29,12 @@ static bool trans_ctz(DisasContext *ctx, arg_ctz *a) return gen_cxz(ctx, a, &tcg_gen_ctzi_tl); } +static bool trans_pcnt(DisasContext *ctx, arg_pcnt *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_unary(ctx, a, &tcg_gen_ctpop_tl); +} + /* RV64-only instructions */ #ifdef TARGET_RISCV64 @@ -44,4 +50,10 @@ static bool trans_ctzw(DisasContext *ctx, arg_ctzw *a) return gen_cxzw(ctx, a, &tcg_gen_ctzi_i32); } +static bool trans_pcntw(DisasContext *ctx, arg_pcntw *a) +{ + REQUIRE_EXT(ctx, RVB); + return gen_unary(ctx, a, &gen_pcntw); +} + #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 20b47f7a660..97e5899750e 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -736,6 +736,12 @@ static bool gen_cxzw(DisasContext *ctx, arg_r2 *a, return true; } +static void gen_pcntw(TCGv ret, TCGv arg1) +{ + tcg_gen_ext32u_tl(arg1, arg1); + tcg_gen_ctpop_tl(ret, arg1); +} + #endif static bool gen_arith(DisasContext *ctx, arg_r *a, @@ -793,6 +799,21 @@ static bool gen_cxz(DisasContext *ctx, arg_r2 *a, return true; } +static bool gen_unary(DisasContext *ctx, arg_r2 *a, + void(*func)(TCGv, TCGv)) +{ + TCGv source; + source = tcg_temp_new(); + + gen_get_gpr(source, a->rs1); + + (*func)(source, source); + + gen_set_gpr(a->rd, source); + tcg_temp_free(source); + return true; +} + /* Include insn module translation function */ #include "insn_trans/trans_rvi.c.inc" #include "insn_trans/trans_rvm.c.inc" -- 2.17.1