From: remi.denis.courmont@huawei.com
To: qemu-arm@nongnu.org
Cc: qemu-devel@nongnu.org
Subject: [PATCH 01/17] target/arm: remove redundant tests
Date: Mon, 23 Nov 2020 10:02:21 +0200 [thread overview]
Message-ID: <20201123080237.18465-1-remi.denis.courmont@huawei.com> (raw)
In-Reply-To: <3333301.iIbC2pHGDl@basile.remlab.net>
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
In this context, the HCR value is the effective value, and thus is
zero in secure mode. The tests for HCR.{F,I}MO are sufficient.
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.c | 8 ++++----
target/arm/helper.c | 10 ++++------
2 files changed, 8 insertions(+), 10 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 07492e9f9a..48b34080ce 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -447,14 +447,14 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
break;
case EXCP_VFIQ:
- if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
- /* VFIQs are only taken when hypervized and non-secure. */
+ if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
+ /* VFIQs are only taken when hypervized. */
return false;
}
return !(env->daif & PSTATE_F);
case EXCP_VIRQ:
- if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
- /* VIRQs are only taken when hypervized and non-secure. */
+ if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
+ /* VIRQs are only taken when hypervized. */
return false;
}
return !(env->daif & PSTATE_I);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 11b0803df7..346dc91a91 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -2083,13 +2083,11 @@ static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
CPUState *cs = env_cpu(env);
- uint64_t hcr_el2 = arm_hcr_el2_eff(env);
+ bool el1 = arm_current_el(env) == 1;
+ uint64_t hcr_el2 = el1 ? arm_hcr_el2_eff(env) : 0;
uint64_t ret = 0;
- bool allow_virt = (arm_current_el(env) == 1 &&
- (!arm_is_secure_below_el3(env) ||
- (env->cp15.scr_el3 & SCR_EEL2)));
- if (allow_virt && (hcr_el2 & HCR_IMO)) {
+ if (hcr_el2 & HCR_IMO) {
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
ret |= CPSR_I;
}
@@ -2099,7 +2097,7 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
}
}
- if (allow_virt && (hcr_el2 & HCR_FMO)) {
+ if (hcr_el2 & HCR_FMO) {
if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
ret |= CPSR_F;
}
--
2.29.2
next prev parent reply other threads:[~2020-11-23 8:07 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-23 8:01 [PATCHv3 00/17] ARMv8.4 Secure EL2 Rémi Denis-Courmont
2020-11-23 8:02 ` remi.denis.courmont [this message]
2020-11-23 8:02 ` [PATCH 02/17] target/arm: add arm_is_el2_enabled() helper remi.denis.courmont
2020-11-23 8:02 ` [PATCH 03/17] target/arm: use arm_is_el2_enabled() where applicable remi.denis.courmont
2020-11-23 8:02 ` [PATCH 04/17] target/arm: use arm_hcr_el2_eff() " remi.denis.courmont
2020-11-23 8:02 ` [PATCH 05/17] target/arm: factor MDCR_EL2 common handling remi.denis.courmont
2020-11-23 8:02 ` [PATCH 06/17] target/arm: declare new AA64PFR0 bit-fields remi.denis.courmont
2020-11-23 8:02 ` [PATCH 07/17] target/arm: add 64-bit S-EL2 to EL exception table remi.denis.courmont
2020-11-23 8:02 ` [PATCH 08/17] target/arm: return the stage 2 index for stage 1 remi.denis.courmont
2020-11-23 8:02 ` [PATCH 09/17] target/arm: add MMU stage 1 for Secure EL2 remi.denis.courmont
2020-11-23 8:02 ` [PATCH 10/17] target/arm: add ARMv8.4-SEL2 system registers remi.denis.courmont
2020-11-23 8:02 ` [PATCH 11/17] target/arm: do S1_ptw_translate() before address space lookup remi.denis.courmont
2020-11-23 8:02 ` [PATCH 12/17] target/arm: secure stage 2 translation regime remi.denis.courmont
2020-11-23 8:02 ` [PATCH 13/17] target/arm: handle VMID change in secure state remi.denis.courmont
2020-11-23 8:02 ` [PATCH 14/17] target/arm: set HPFAR_EL2.NS on secure stage 2 faults remi.denis.courmont
2020-11-23 8:02 ` [PATCH 15/17] target/arm: add ARMv8.4-SEL2 extension remi.denis.courmont
2020-11-23 8:02 ` [PATCH 16/17] target/arm: enable Secure EL2 in max CPU remi.denis.courmont
2020-11-23 8:02 ` [PATCH 17/17] target/arm: refactor vae1_tlbmask() remi.denis.courmont
2020-12-01 16:54 ` [PATCHv3 00/17] ARMv8.4 Secure EL2 Peter Maydell
2020-12-01 17:20 ` Rémi Denis-Courmont
2020-12-01 18:23 ` Peter Maydell
2020-12-01 18:37 ` Rémi Denis-Courmont
2020-12-08 14:11 ` Alex Bennée
2020-12-18 9:45 ` Rémi Denis-Courmont
-- strict thread matches above, loose matches on Subject: below --
2020-11-09 13:56 [PATCHv2 00/17] ARM Secure EL2 extension Rémi Denis-Courmont
2020-11-09 14:10 ` [PATCH 01/17] target/arm: remove redundant tests remi.denis.courmont
2020-11-13 21:18 ` Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20201123080237.18465-1-remi.denis.courmont@huawei.com \
--to=remi.denis.courmont@huawei.com \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.