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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id a62sm35673893wmh.40.2020.12.14.10.37.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:37:51 -0800 (PST) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Jiaxun Yang , Laurent Vivier , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Subject: [PATCH v2 02/16] target/mips: Extract FPU helpers to 'fpu_helper.h' Date: Mon, 14 Dec 2020 19:37:25 +0100 Message-Id: <20201214183739.500368-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Extract FPU specific helpers from "internal.h" to "fpu_helper.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201120210844.2625602-2-f4bug@amsat.org> --- target/mips/fpu_helper.h | 59 ++++++++++++++++++++++++++++++++ target/mips/internal.h | 49 -------------------------- linux-user/mips/cpu_loop.c | 1 + target/mips/fpu_helper.c | 1 + target/mips/gdbstub.c | 1 + target/mips/kvm.c | 1 + target/mips/machine.c | 1 + target/mips/msa_helper.c | 1 + target/mips/op_helper.c | 2 +- target/mips/translate.c | 1 + target/mips/translate_init.c.inc | 2 ++ 11 files changed, 69 insertions(+), 50 deletions(-) create mode 100644 target/mips/fpu_helper.h diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h new file mode 100644 index 00000000000..1c2d6d35a71 --- /dev/null +++ b/target/mips/fpu_helper.h @@ -0,0 +1,59 @@ +/* + * Helpers for emulation of FPU-related MIPS instructions. + * + * Copyright (C) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#include "fpu/softfloat-helpers.h" +#include "cpu.h" + +extern const FloatRoundMode ieee_rm[4]; + +uint32_t float_class_s(uint32_t arg, float_status *fst); +uint64_t float_class_d(uint64_t arg, float_status *fst); + +static inline void restore_rounding_mode(CPUMIPSState *env) +{ + set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], + &env->active_fpu.fp_status); +} + +static inline void restore_flush_mode(CPUMIPSState *env) +{ + set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0, + &env->active_fpu.fp_status); +} + +static inline void restore_snan_bit_mode(CPUMIPSState *env) +{ + set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, + &env->active_fpu.fp_status); +} + +static inline void restore_fp_status(CPUMIPSState *env) +{ + restore_rounding_mode(env); + restore_flush_mode(env); + restore_snan_bit_mode(env); +} + +/* MSA */ + +enum CPUMIPSMSADataFormat { + DF_BYTE = 0, + DF_HALF, + DF_WORD, + DF_DOUBLE +}; + +static inline void restore_msa_fp_status(CPUMIPSState *env) +{ + float_status *status = &env->active_tc.msa_fp_status; + int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM; + bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0; + + set_float_rounding_mode(ieee_rm[rounding_mode], status); + set_flush_to_zero(flush_to_zero, status); + set_flush_inputs_to_zero(flush_to_zero, status); +} diff --git a/target/mips/internal.h b/target/mips/internal.h index e4d2d9f44f9..24d9f0d6a5c 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -9,7 +9,6 @@ #define MIPS_INTERNAL_H #include "exec/memattrs.h" -#include "fpu/softfloat-helpers.h" /* * MMU types, the first four entries have the same layout as the @@ -75,13 +74,6 @@ struct mips_def_t { extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; -enum CPUMIPSMSADataFormat { - DF_BYTE = 0, - DF_HALF, - DF_WORD, - DF_DOUBLE -}; - void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags); @@ -220,49 +212,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool probe, uintptr_t retaddr); /* op_helper.c */ -uint32_t float_class_s(uint32_t arg, float_status *fst); -uint64_t float_class_d(uint64_t arg, float_status *fst); - -extern const FloatRoundMode ieee_rm[4]; - void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask); -static inline void restore_rounding_mode(CPUMIPSState *env) -{ - set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], - &env->active_fpu.fp_status); -} - -static inline void restore_flush_mode(CPUMIPSState *env) -{ - set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0, - &env->active_fpu.fp_status); -} - -static inline void restore_snan_bit_mode(CPUMIPSState *env) -{ - set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, - &env->active_fpu.fp_status); -} - -static inline void restore_fp_status(CPUMIPSState *env) -{ - restore_rounding_mode(env); - restore_flush_mode(env); - restore_snan_bit_mode(env); -} - -static inline void restore_msa_fp_status(CPUMIPSState *env) -{ - float_status *status = &env->active_tc.msa_fp_status; - int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM; - bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0; - - set_float_rounding_mode(ieee_rm[rounding_mode], status); - set_flush_to_zero(flush_to_zero, status); - set_flush_inputs_to_zero(flush_to_zero, status); -} - static inline void restore_pamask(CPUMIPSState *env) { if (env->hflags & MIPS_HFLAG_ELPA) { diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index cfe7ba5c47d..b58dbeb83d1 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -23,6 +23,7 @@ #include "cpu_loop-common.h" #include "elf.h" #include "internal.h" +#include "fpu_helper.h" # ifdef TARGET_ABI_MIPSO32 # define MIPS_SYSCALL_NUMBER_UNUSED -1 diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index bdb65065ee7..a3c05160b35 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -27,6 +27,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" +#include "fpu_helper.h" /* Complex FPU operations which may need stack space. */ diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index e39f8d75cf0..f1c2a2cf6d6 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "internal.h" #include "exec/gdbstub.h" +#include "fpu_helper.h" int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 477692566a4..a5b6fe35dbc 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -24,6 +24,7 @@ #include "sysemu/runstate.h" #include "kvm_mips.h" #include "hw/boards.h" +#include "fpu_helper.h" #define DEBUG_KVM 0 diff --git a/target/mips/machine.c b/target/mips/machine.c index 5b23e3e912a..a4ea67c2980 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -2,6 +2,7 @@ #include "cpu.h" #include "internal.h" #include "migration/cpu.h" +#include "fpu_helper.h" static int cpu_post_load(void *opaque, int version_id) { diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 249f0fdad80..b89b4c44902 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" +#include "fpu_helper.h" /* Data format min and max values */ #define DF_BITS(df) (1 << ((df) + 3)) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 5aa97902e98..3386b8228e9 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -24,7 +24,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/memop.h" - +#include "fpu_helper.h" /*****************************************************************************/ /* Exceptions processing helpers */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 19933b7868c..d2614796214 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -35,6 +35,7 @@ #include "exec/translator.h" #include "exec/log.h" #include "qemu/qemu-print.h" +#include "fpu_helper.h" #define MIPS_DEBUG_DISAS 0 diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc index f72fee3b40a..915277dd1f6 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -18,6 +18,8 @@ * License along with this library; if not, see . */ +#include "fpu_helper.h" + /* CPU / CPU family specific config register values. */ /* Have config1, uncached coherency */ -- 2.26.2 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNWANTED_LANGUAGE_BODY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 141D8C4361B for ; Mon, 14 Dec 2020 18:45:04 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9D97822573 for ; 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[88.21.206.101]) by smtp.gmail.com with ESMTPSA id a62sm35673893wmh.40.2020.12.14.10.37.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Dec 2020 10:37:51 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 02/16] target/mips: Extract FPU helpers to 'fpu_helper.h' Date: Mon, 14 Dec 2020 19:37:25 +0100 Message-Id: <20201214183739.500368-3-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201214183739.500368-1-f4bug@amsat.org> References: <20201214183739.500368-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Aleksandar Rikalo , kvm@vger.kernel.org, Huacai Chen , Richard Henderson , Laurent Vivier , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Extract FPU specific helpers from "internal.h" to "fpu_helper.h". Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20201120210844.2625602-2-f4bug@amsat.org> --- target/mips/fpu_helper.h | 59 ++++++++++++++++++++++++++++++++ target/mips/internal.h | 49 -------------------------- linux-user/mips/cpu_loop.c | 1 + target/mips/fpu_helper.c | 1 + target/mips/gdbstub.c | 1 + target/mips/kvm.c | 1 + target/mips/machine.c | 1 + target/mips/msa_helper.c | 1 + target/mips/op_helper.c | 2 +- target/mips/translate.c | 1 + target/mips/translate_init.c.inc | 2 ++ 11 files changed, 69 insertions(+), 50 deletions(-) create mode 100644 target/mips/fpu_helper.h diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h new file mode 100644 index 00000000000..1c2d6d35a71 --- /dev/null +++ b/target/mips/fpu_helper.h @@ -0,0 +1,59 @@ +/* + * Helpers for emulation of FPU-related MIPS instructions. + * + * Copyright (C) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#include "fpu/softfloat-helpers.h" +#include "cpu.h" + +extern const FloatRoundMode ieee_rm[4]; + +uint32_t float_class_s(uint32_t arg, float_status *fst); +uint64_t float_class_d(uint64_t arg, float_status *fst); + +static inline void restore_rounding_mode(CPUMIPSState *env) +{ + set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], + &env->active_fpu.fp_status); +} + +static inline void restore_flush_mode(CPUMIPSState *env) +{ + set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0, + &env->active_fpu.fp_status); +} + +static inline void restore_snan_bit_mode(CPUMIPSState *env) +{ + set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, + &env->active_fpu.fp_status); +} + +static inline void restore_fp_status(CPUMIPSState *env) +{ + restore_rounding_mode(env); + restore_flush_mode(env); + restore_snan_bit_mode(env); +} + +/* MSA */ + +enum CPUMIPSMSADataFormat { + DF_BYTE = 0, + DF_HALF, + DF_WORD, + DF_DOUBLE +}; + +static inline void restore_msa_fp_status(CPUMIPSState *env) +{ + float_status *status = &env->active_tc.msa_fp_status; + int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM; + bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0; + + set_float_rounding_mode(ieee_rm[rounding_mode], status); + set_flush_to_zero(flush_to_zero, status); + set_flush_inputs_to_zero(flush_to_zero, status); +} diff --git a/target/mips/internal.h b/target/mips/internal.h index e4d2d9f44f9..24d9f0d6a5c 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -9,7 +9,6 @@ #define MIPS_INTERNAL_H #include "exec/memattrs.h" -#include "fpu/softfloat-helpers.h" /* * MMU types, the first four entries have the same layout as the @@ -75,13 +74,6 @@ struct mips_def_t { extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; -enum CPUMIPSMSADataFormat { - DF_BYTE = 0, - DF_HALF, - DF_WORD, - DF_DOUBLE -}; - void mips_cpu_do_interrupt(CPUState *cpu); bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags); @@ -220,49 +212,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, bool probe, uintptr_t retaddr); /* op_helper.c */ -uint32_t float_class_s(uint32_t arg, float_status *fst); -uint64_t float_class_d(uint64_t arg, float_status *fst); - -extern const FloatRoundMode ieee_rm[4]; - void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask); -static inline void restore_rounding_mode(CPUMIPSState *env) -{ - set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], - &env->active_fpu.fp_status); -} - -static inline void restore_flush_mode(CPUMIPSState *env) -{ - set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0, - &env->active_fpu.fp_status); -} - -static inline void restore_snan_bit_mode(CPUMIPSState *env) -{ - set_snan_bit_is_one((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) == 0, - &env->active_fpu.fp_status); -} - -static inline void restore_fp_status(CPUMIPSState *env) -{ - restore_rounding_mode(env); - restore_flush_mode(env); - restore_snan_bit_mode(env); -} - -static inline void restore_msa_fp_status(CPUMIPSState *env) -{ - float_status *status = &env->active_tc.msa_fp_status; - int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM; - bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0; - - set_float_rounding_mode(ieee_rm[rounding_mode], status); - set_flush_to_zero(flush_to_zero, status); - set_flush_inputs_to_zero(flush_to_zero, status); -} - static inline void restore_pamask(CPUMIPSState *env) { if (env->hflags & MIPS_HFLAG_ELPA) { diff --git a/linux-user/mips/cpu_loop.c b/linux-user/mips/cpu_loop.c index cfe7ba5c47d..b58dbeb83d1 100644 --- a/linux-user/mips/cpu_loop.c +++ b/linux-user/mips/cpu_loop.c @@ -23,6 +23,7 @@ #include "cpu_loop-common.h" #include "elf.h" #include "internal.h" +#include "fpu_helper.h" # ifdef TARGET_ABI_MIPSO32 # define MIPS_SYSCALL_NUMBER_UNUSED -1 diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c index bdb65065ee7..a3c05160b35 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/fpu_helper.c @@ -27,6 +27,7 @@ #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" +#include "fpu_helper.h" /* Complex FPU operations which may need stack space. */ diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index e39f8d75cf0..f1c2a2cf6d6 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "internal.h" #include "exec/gdbstub.h" +#include "fpu_helper.h" int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/mips/kvm.c b/target/mips/kvm.c index 477692566a4..a5b6fe35dbc 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -24,6 +24,7 @@ #include "sysemu/runstate.h" #include "kvm_mips.h" #include "hw/boards.h" +#include "fpu_helper.h" #define DEBUG_KVM 0 diff --git a/target/mips/machine.c b/target/mips/machine.c index 5b23e3e912a..a4ea67c2980 100644 --- a/target/mips/machine.c +++ b/target/mips/machine.c @@ -2,6 +2,7 @@ #include "cpu.h" #include "internal.h" #include "migration/cpu.h" +#include "fpu_helper.h" static int cpu_post_load(void *opaque, int version_id) { diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 249f0fdad80..b89b4c44902 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" +#include "fpu_helper.h" /* Data format min and max values */ #define DF_BITS(df) (1 << ((df) + 3)) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 5aa97902e98..3386b8228e9 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -24,7 +24,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/memop.h" - +#include "fpu_helper.h" /*****************************************************************************/ /* Exceptions processing helpers */ diff --git a/target/mips/translate.c b/target/mips/translate.c index 19933b7868c..d2614796214 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -35,6 +35,7 @@ #include "exec/translator.h" #include "exec/log.h" #include "qemu/qemu-print.h" +#include "fpu_helper.h" #define MIPS_DEBUG_DISAS 0 diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.c.inc index f72fee3b40a..915277dd1f6 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -18,6 +18,8 @@ * License along with this library; if not, see . */ +#include "fpu_helper.h" + /* CPU / CPU family specific config register values. */ /* Have config1, uncached coherency */ -- 2.26.2