From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Cc: ulf.hansson@linaro.org, linux-mmc@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH v2 2/2] mmc: renesas_internal_dmac: add pre_req and post_req support
Date: Wed, 16 Dec 2020 15:11:31 +0100 [thread overview]
Message-ID: <20201216141131.GA4563@ninjato> (raw)
In-Reply-To: <1608114572-1892-3-git-send-email-yoshihiro.shimoda.uh@renesas.com>
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On Wed, Dec 16, 2020 at 07:29:32PM +0900, Yoshihiro Shimoda wrote:
> Add pre_req and post_req support to improve performance.
>
> Inspired by a patch in the BSP by Masaharu Hayakawa.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
So, I tested this on H3 ES2.0 and M3-N with interesting results. H3
ES2.0 has a significant speedup:
with: 254MB/s, without 207MB/s
M3-N speedup is smaller but general throughput is much better:
with: 262MB/s, without 250MB/s
Same kernel, both systems idle otherwise. I don't think it has to do
with the number of CPU cores, but more that the SDHI revision is a tad
newer maybe?
Patch looks good, too:
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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next prev parent reply other threads:[~2020-12-16 14:12 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-16 10:29 [PATCH v2 0/2] mmc: renesas_internal_dmac: add pre_req and post_req support Yoshihiro Shimoda
2020-12-16 10:29 ` [PATCH v2 1/2] mmc: renesas_sdhi_internal_dmac: Fix DMA buffer alignment from 8 to 128-bytes Yoshihiro Shimoda
2020-12-17 7:09 ` Wolfram Sang
2020-12-16 10:29 ` [PATCH v2 2/2] mmc: renesas_internal_dmac: add pre_req and post_req support Yoshihiro Shimoda
2020-12-16 14:11 ` Wolfram Sang [this message]
2021-01-13 11:24 ` [PATCH v2 0/2] " Ulf Hansson
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