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From: Siew Chin Lim <elly.siew.chin.lim@intel.com>
To: u-boot@lists.denx.de
Subject: [v5 12/18] arm: socfpga: soc64: Add ATF support for FPGA reconfig driver
Date: Tue, 22 Dec 2020 00:49:36 +0800	[thread overview]
Message-ID: <20201221164942.11640-13-elly.siew.chin.lim@intel.com> (raw)
In-Reply-To: <20201221164942.11640-1-elly.siew.chin.lim@intel.com>

From: Chee Hong Ang <chee.hong.ang@intel.com>

In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
---
 drivers/fpga/intel_sdm_mb.c | 139 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 139 insertions(+)

diff --git a/drivers/fpga/intel_sdm_mb.c b/drivers/fpga/intel_sdm_mb.c
index 9a1dc2c0c8..f5fd9a14c2 100644
--- a/drivers/fpga/intel_sdm_mb.c
+++ b/drivers/fpga/intel_sdm_mb.c
@@ -8,11 +8,149 @@
 #include <log.h>
 #include <watchdog.h>
 #include <asm/arch/mailbox_s10.h>
+#include <asm/arch/smc_api.h>
 #include <linux/delay.h>
+#include <linux/intel-smc.h>
 
 #define RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS		60000
 #define RECONFIG_STATUS_INTERVAL_DELAY_US		1000000
 
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_ATF)
+
+#define BITSTREAM_CHUNK_SIZE				0xFFFF0
+#define RECONFIG_STATUS_POLL_RETRY_MAX			100
+
+/*
+ * Polling the FPGA configuration status.
+ * Return 0 for success, non-zero for error.
+ */
+static int reconfig_status_polling_resp(void)
+{
+	int ret;
+	unsigned long start = get_timer(0);
+
+	while (1) {
+		ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_ISDONE, NULL, 0,
+				 NULL, 0);
+
+		if (!ret)
+			return 0;	/* configuration success */
+
+		if (ret != INTEL_SIP_SMC_STATUS_BUSY)
+			return ret;
+
+		if (get_timer(start) > RECONFIG_STATUS_POLL_RESP_TIMEOUT_MS)
+			return -ETIMEDOUT;	/* time out */
+
+		puts(".");
+		udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+		WATCHDOG_RESET();
+	}
+
+	return -ETIMEDOUT;
+}
+
+static int send_bitstream(const void *rbf_data, size_t rbf_size)
+{
+	int i;
+	u64 res_buf[3];
+	u64 args[2];
+	u32 xfer_count = 0;
+	int ret, wr_ret = 0, retry = 0;
+	size_t buf_size = (rbf_size > BITSTREAM_CHUNK_SIZE) ?
+				BITSTREAM_CHUNK_SIZE : rbf_size;
+
+	while (rbf_size || xfer_count) {
+		if (!wr_ret && rbf_size) {
+			args[0] = (u64)rbf_data;
+			args[1] = buf_size;
+			wr_ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_WRITE,
+					    args, 2, NULL, 0);
+
+			debug("wr_ret = %d, rbf_data = %p, buf_size = %08lx\n",
+			      wr_ret, rbf_data, buf_size);
+
+			if (wr_ret)
+				continue;
+
+			rbf_size -= buf_size;
+			rbf_data += buf_size;
+
+			if (buf_size >= rbf_size)
+				buf_size = rbf_size;
+
+			xfer_count++;
+			puts(".");
+		} else {
+			ret = invoke_smc(
+				INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE,
+				NULL, 0, res_buf, ARRAY_SIZE(res_buf));
+			if (!ret) {
+				for (i = 0; i < ARRAY_SIZE(res_buf); i++) {
+					if (!res_buf[i])
+						break;
+					xfer_count--;
+					wr_ret = 0;
+					retry = 0;
+				}
+			} else if (ret !=
+				   INTEL_SIP_SMC_STATUS_BUSY)
+				return ret;
+			else if (!xfer_count)
+				return INTEL_SIP_SMC_STATUS_ERROR;
+
+			if (++retry >= RECONFIG_STATUS_POLL_RETRY_MAX)
+				return -ETIMEDOUT;
+
+			udelay(20000);
+		}
+		WATCHDOG_RESET();
+	}
+
+	return 0;
+}
+
+/*
+ * This is the interface used by FPGA driver.
+ * Return 0 for success, non-zero for error.
+ */
+int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
+{
+	int ret;
+	u64 arg = 1;
+
+	debug("Invoking FPGA_CONFIG_START...\n");
+
+	ret = invoke_smc(INTEL_SIP_SMC_FPGA_CONFIG_START, &arg, 1, NULL, 0);
+
+	if (ret) {
+		puts("Failure in RECONFIG mailbox command!\n");
+		return ret;
+	}
+
+	ret = send_bitstream(rbf_data, rbf_size);
+	if (ret) {
+		puts("Error sending bitstream!\n");
+		return ret;
+	}
+
+	/* Make sure we don't send MBOX_RECONFIG_STATUS too fast */
+	udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
+
+	debug("Polling with MBOX_RECONFIG_STATUS...\n");
+	ret = reconfig_status_polling_resp();
+	if (ret) {
+		puts("FPGA reconfiguration failed!");
+		return ret;
+	}
+
+	puts("FPGA reconfiguration OK!\n");
+
+	return ret;
+}
+
+#else
+
 static const struct mbox_cfgstat_state {
 	int			err_no;
 	const char		*error_name;
@@ -286,3 +424,4 @@ int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 
 	return ret;
 }
+#endif
-- 
2.13.0

  parent reply	other threads:[~2020-12-21 16:49 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-21 16:49 [v5 00/18] Enable ARM Trusted Firmware for U-Boot Siew Chin Lim
2020-12-21 16:49 ` [v5 01/18] arm: socfpga: Add function for checking description from FIT image Siew Chin Lim
2020-12-21 16:49 ` [v5 02/18] arm: socfpga: soc64: Load FIT image with ATF support Siew Chin Lim
2020-12-21 16:49 ` [v5 03/18] arm: socfpga: soc64: Override 'lowlevel_init' to support ATF Siew Chin Lim
2020-12-21 16:49 ` [v5 04/18] arm: socfpga: Disable "spin-table" method for booting Linux Siew Chin Lim
2020-12-21 16:49 ` [v5 05/18] arm: socfpga: soc64: Add SMC helper function for Intel SOCFPGA (64bits) Siew Chin Lim
2020-12-21 16:49 ` [v5 06/18] arm: socfpga: soc64: Define SMC function identifiers for PSCI SiP services Siew Chin Lim
2020-12-21 16:49 ` [v5 07/18] arm: socfpga: Add secure register access helper functions for SoC 64bits Siew Chin Lim
2020-12-23  3:28   ` Tan, Ley Foon
2020-12-21 16:49 ` [v5 08/18] mmc: dwmmc: Change designware MMC 'clksel' callback function to return status Siew Chin Lim
2020-12-22 23:49   ` Jaehoon Chung
2020-12-23  3:31   ` Tan, Ley Foon
2020-12-21 16:49 ` [v5 09/18] mmc: dwmmc: socfpga: Add ATF support for MMC driver Siew Chin Lim
2020-12-22 23:50   ` Jaehoon Chung
2020-12-23  3:33   ` Tan, Ley Foon
2020-12-21 16:49 ` [v5 10/18] net: designware: socfpga: Add ATF support for MAC driver Siew Chin Lim
2020-12-23  3:42   ` Tan, Ley Foon
2020-12-21 16:49 ` [v5 11/18] arm: socfpga: soc64: Add ATF support for Reset Manager driver Siew Chin Lim
2020-12-21 16:49 ` Siew Chin Lim [this message]
2020-12-21 16:49 ` [v5 13/18] arm: socfpga: mailbox: Add 'SYSTEM_RESET' PSCI support to mbox_reset_cold() Siew Chin Lim
2020-12-21 16:49 ` [v5 14/18] arm: socfpga: soc64: SSBL shall not setup stack on OCRAM Siew Chin Lim
2020-12-21 16:49 ` [v5 15/18] arm: socfpga: soc64: Skip handoff data access in SSBL Siew Chin Lim
2020-12-21 16:49 ` [v5 16/18] arm: socfpga: dts: soc64: Add binman node of FIT image with ATF support Siew Chin Lim
2020-12-23  3:45   ` Tan, Ley Foon
2020-12-29  3:31   ` Simon Glass
2020-12-21 16:49 ` [v5 17/18] arm: socfpga: soc64: Enable FIT image generation using binman Siew Chin Lim
2020-12-23  3:48   ` Tan, Ley Foon
2020-12-29  3:31   ` Simon Glass
2020-12-21 16:49 ` [v5 18/18] configs: socfpga: Add defconfig for Agilex and Stratix 10 with ATF support Siew Chin Lim

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