From: Ulrich Hecht <uli+renesas@fpond.eu>
To: linux-renesas-soc@vger.kernel.org
Cc: wsa@the-dreams.de, geert@linux-m68k.org, hoai.luu.ub@renesas.com,
Ulrich Hecht <uli+renesas@fpond.eu>,
Geert Uytterhoeven <geert+renesas@glider.be>
Subject: [PATCH v2 06/12] pinctrl: renesas: r8a779a0: Add INTC-EX pins, groups and function
Date: Mon, 21 Dec 2020 17:55:35 +0100 [thread overview]
Message-ID: <20201221165541.27679-7-uli+renesas@fpond.eu> (raw)
In-Reply-To: <20201221165541.27679-1-uli+renesas@fpond.eu>
Add pins, groups, and function for the Interrupt Controller for External
Devices (INTC-EX) on the R-Car R8A779A0 (V3U) SoC.
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pinctrl/renesas/pfc-r8a779a0.c | 62 ++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index be8afb13cce6..a141fd1ee49c 100644
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -1965,6 +1965,50 @@ static const unsigned int i2c6_mux[] = {
SDA6_MARK, SCL6_MARK,
};
+/* - INTC-EX ---------------------------------------------------------------- */
+static const unsigned int intc_ex_irq0_pins[] = {
+ /* IRQ0 */
+ RCAR_GP_PIN(1, 24),
+};
+static const unsigned int intc_ex_irq0_mux[] = {
+ IRQ0_MARK,
+};
+static const unsigned int intc_ex_irq1_pins[] = {
+ /* IRQ1 */
+ RCAR_GP_PIN(1, 25),
+};
+static const unsigned int intc_ex_irq1_mux[] = {
+ IRQ1_MARK,
+};
+static const unsigned int intc_ex_irq2_pins[] = {
+ /* IRQ2 */
+ RCAR_GP_PIN(1, 26),
+};
+static const unsigned int intc_ex_irq2_mux[] = {
+ IRQ2_MARK,
+};
+static const unsigned int intc_ex_irq3_pins[] = {
+ /* IRQ3 */
+ RCAR_GP_PIN(1, 27),
+};
+static const unsigned int intc_ex_irq3_mux[] = {
+ IRQ3_MARK,
+};
+static const unsigned int intc_ex_irq4_pins[] = {
+ /* IRQ4 */
+ RCAR_GP_PIN(2, 14),
+};
+static const unsigned int intc_ex_irq4_mux[] = {
+ IRQ4_MARK,
+};
+static const unsigned int intc_ex_irq5_pins[] = {
+ /* IRQ5 */
+ RCAR_GP_PIN(2, 15),
+};
+static const unsigned int intc_ex_irq5_mux[] = {
+ IRQ5_MARK,
+};
+
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins[] = {
/* RX0, TX0 */
@@ -2170,6 +2214,13 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP(i2c5),
SH_PFC_PIN_GROUP(i2c6),
+ SH_PFC_PIN_GROUP(intc_ex_irq0),
+ SH_PFC_PIN_GROUP(intc_ex_irq1),
+ SH_PFC_PIN_GROUP(intc_ex_irq2),
+ SH_PFC_PIN_GROUP(intc_ex_irq3),
+ SH_PFC_PIN_GROUP(intc_ex_irq4),
+ SH_PFC_PIN_GROUP(intc_ex_irq5),
+
SH_PFC_PIN_GROUP(scif0_data),
SH_PFC_PIN_GROUP(scif0_clk),
SH_PFC_PIN_GROUP(scif0_ctrl),
@@ -2353,6 +2404,15 @@ static const char * const i2c6_groups[] = {
"i2c6",
};
+static const char * const intc_ex_groups[] = {
+ "intc_ex_irq0",
+ "intc_ex_irq1",
+ "intc_ex_irq2",
+ "intc_ex_irq3",
+ "intc_ex_irq4",
+ "intc_ex_irq5",
+};
+
static const char * const scif0_groups[] = {
"scif0_data",
"scif0_clk",
@@ -2415,6 +2475,8 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION(i2c5),
SH_PFC_FUNCTION(i2c6),
+ SH_PFC_FUNCTION(intc_ex),
+
SH_PFC_FUNCTION(scif0),
SH_PFC_FUNCTION(scif1),
SH_PFC_FUNCTION(scif3),
--
2.20.1
next prev parent reply other threads:[~2020-12-21 16:59 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-21 16:55 [PATCH v2 00/12] pinctrl: renesas: R8A779A0 (V3U) device support Ulrich Hecht
2020-12-21 16:55 ` [PATCH v2 01/12] pinctrl: renesas: r8a779a0: Add I2C pins, groups and functions Ulrich Hecht
2020-12-22 10:08 ` Geert Uytterhoeven
2020-12-23 16:00 ` Wolfram Sang
2020-12-21 16:55 ` [PATCH v2 02/12] pinctrl: renesas: r8a779a0: Add EtherAVB " Ulrich Hecht
2020-12-22 10:10 ` Geert Uytterhoeven
2021-01-12 16:59 ` Ulrich Hecht
2020-12-23 16:00 ` Wolfram Sang
2020-12-21 16:55 ` [PATCH v2 03/12] pinctrl: renesas: r8a779a0: Add CANFD " Ulrich Hecht
2020-12-22 10:05 ` Geert Uytterhoeven
2020-12-21 16:55 ` [PATCH v2 04/12] pinctrl: renesas: r8a779a0: Add DU pins, groups and function Ulrich Hecht
2020-12-21 16:55 ` [PATCH v2 05/12] pinctrl: renesas: r8a779a0: Add HSCIF pins, groups and functions Ulrich Hecht
2020-12-28 12:15 ` Wolfram Sang
2020-12-21 16:55 ` Ulrich Hecht [this message]
2020-12-21 16:55 ` [PATCH v2 07/12] pinctrl: renesas: r8a779a0: Add MMC " Ulrich Hecht
2020-12-27 18:13 ` Wolfram Sang
2020-12-21 16:55 ` [PATCH v2 08/12] pinctrl: renesas: r8a779a0: Add MSIOF " Ulrich Hecht
2020-12-21 16:55 ` [PATCH v2 09/12] pinctrl: renesas: r8a779a0: Add PWM " Ulrich Hecht
2020-12-21 16:55 ` [PATCH v2 10/12] pinctrl: renesas: r8a779a0: Add QSPI pins, groups, " Ulrich Hecht
2020-12-21 16:55 ` [PATCH v2 11/12] pinctrl: renesas: r8a779a0: Add TMU pins, groups " Ulrich Hecht
2020-12-22 10:20 ` Geert Uytterhoeven
2020-12-21 16:55 ` [PATCH v2 12/12] pinctrl: renesas: r8a779a0: Add TPU " Ulrich Hecht
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