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From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: linux-renesas-soc@vger.kernel.org
Cc: Wolfram Sang <wsa+renesas@sang-engineering.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 2/6] clk: renesas: rcar-gen3: remove cpg_quirks access when registering SD clock
Date: Sun, 27 Dec 2020 18:41:56 +0100	[thread overview]
Message-ID: <20201227174202.40834-3-wsa+renesas@sang-engineering.com> (raw)
In-Reply-To: <20201227174202.40834-1-wsa+renesas@sang-engineering.com>

We want to reuse SD clock handling for other SoCs and, thus, need to
generalize it. So, don't access cpg_quirks in that realm.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 drivers/clk/renesas/rcar-gen3-cpg.c | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 063b61151488..3b2eb46b7e58 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -375,15 +375,9 @@ static const struct clk_ops cpg_sd_clock_ops = {
 	.set_rate = cpg_sd_clock_set_rate,
 };
 
-static u32 cpg_quirks __initdata;
-
-#define PLL_ERRATA	BIT(0)		/* Missing PLL0/2/4 post-divider */
-#define RCKCR_CKSEL	BIT(1)		/* Manual RCLK parent selection */
-#define SD_SKIP_FIRST	BIT(2)		/* Skip first clock in SD table */
-
 static struct clk * __init cpg_sd_clk_register(const char *name,
 	void __iomem *base, unsigned int offset, const char *parent_name,
-	struct raw_notifier_head *notifiers)
+	struct raw_notifier_head *notifiers, bool skip_first)
 {
 	struct clk_init_data init;
 	struct sd_clock *clock;
@@ -405,7 +399,7 @@ static struct clk * __init cpg_sd_clk_register(const char *name,
 	clock->div_table = cpg_sd_div_table;
 	clock->div_num = ARRAY_SIZE(cpg_sd_div_table);
 
-	if (cpg_quirks & SD_SKIP_FIRST) {
+	if (skip_first) {
 		clock->div_table++;
 		clock->div_num--;
 	}
@@ -518,6 +512,12 @@ static struct clk * __init cpg_rpcd2_clk_register(const char *name,
 static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata;
 static unsigned int cpg_clk_extalr __initdata;
 static u32 cpg_mode __initdata;
+static u32 cpg_quirks __initdata;
+
+#define PLL_ERRATA	BIT(0)		/* Missing PLL0/2/4 post-divider */
+#define RCKCR_CKSEL	BIT(1)		/* Manual RCLK parent selection */
+#define SD_SKIP_FIRST	BIT(2)		/* Skip first clock in SD table */
+
 
 static const struct soc_device_attribute cpg_quirks_match[] __initconst = {
 	{
@@ -613,7 +613,8 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev,
 
 	case CLK_TYPE_GEN3_SD:
 		return cpg_sd_clk_register(core->name, base, core->offset,
-					   __clk_get_name(parent), notifiers);
+					   __clk_get_name(parent), notifiers,
+					   cpg_quirks & SD_SKIP_FIRST);
 
 	case CLK_TYPE_GEN3_R:
 		if (cpg_quirks & RCKCR_CKSEL) {
-- 
2.28.0


  parent reply	other threads:[~2020-12-27 17:43 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-27 17:41 [PATCH 0/6] v3u: add SDHI/MMC support Wolfram Sang
2020-12-27 17:41 ` [PATCH 1/6] dt-bindings: mmc: renesas,sdhi: Add r8a779a0 support Wolfram Sang
2021-01-08  3:36   ` Rob Herring
2021-01-08 12:23   ` Geert Uytterhoeven
2021-01-13 11:25   ` Ulf Hansson
2020-12-27 17:41 ` Wolfram Sang [this message]
2021-01-08 12:59   ` [PATCH 2/6] clk: renesas: rcar-gen3: remove cpg_quirks access when registering SD clock Geert Uytterhoeven
2020-12-27 17:41 ` [PATCH 3/6] clk: renesas: rcar-gen3: factor out CPG library Wolfram Sang
2021-01-08 12:59   ` Geert Uytterhoeven
2020-12-27 17:41 ` [PATCH 4/6] clk: renesas: r8a779a0: add SDHI support Wolfram Sang
2021-01-08 12:59   ` Geert Uytterhoeven
2020-12-27 17:41 ` [PATCH 5/6] arm64: dts: renesas: r8a779a0: Add MMC node Wolfram Sang
2020-12-27 17:45   ` Wolfram Sang
2021-01-08 12:47   ` Geert Uytterhoeven
2020-12-27 17:42 ` [PATCH 6/6] arm64: dts: renesas: falcon: Enable MMC Wolfram Sang
2021-01-08 12:59   ` Geert Uytterhoeven
2021-01-19 12:46     ` Wolfram Sang
2021-01-12 11:47   ` Geert Uytterhoeven

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