From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E7B7C433DB for ; Mon, 18 Jan 2021 07:09:31 +0000 (UTC) Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by mail.kernel.org (Postfix) with ESMTP id 017C2223DB for ; Mon, 18 Jan 2021 07:09:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 017C2223DB Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=dev-bounces@dpdk.org Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8E2A3140DA0; Mon, 18 Jan 2021 08:08:34 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id AFBBD140DA0 for ; Mon, 18 Jan 2021 08:08:32 +0100 (CET) IronPort-SDR: WPnqD2okS4HYOWpEyUOhxhGGnytoHlKK/WC6V3yh69Xd2qxaOYWjLkHLpBrxle/90MNKQ7L7Bc pwqiDFCj7SzA== X-IronPort-AV: E=McAfee;i="6000,8403,9867"; a="197460195" X-IronPort-AV: E=Sophos;i="5.79,355,1602572400"; d="scan'208";a="197460195" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2021 23:08:32 -0800 IronPort-SDR: LXUpYk0NR77Yf5AgaWaDs1y1lY5kXi75eUfQ/49mnJudiSBCLFGoQKnb/LZncCK2tIxcMnVADs W1y8qUrqBjzw== X-IronPort-AV: E=Sophos;i="5.79,355,1602572400"; d="scan'208";a="355086884" Received: from intel-npg-odc-srv01.cd.intel.com ([10.240.178.136]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jan 2021 23:08:30 -0800 From: Steve Yang To: dev@dpdk.org Cc: Steve Yang , Harman Kalra Date: Mon, 18 Jan 2021 07:04:17 +0000 Message-Id: <20210118070428.36998-12-stevex.yang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210118070428.36998-1-stevex.yang@intel.com> References: <20210114094537.13661-1-stevex.yang@intel.com> <20210118070428.36998-1-stevex.yang@intel.com> Subject: [dpdk-dev] [PATCH v4 11/22] net/octeontx: fix the jumbo frame flag condition for mtu set X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The jumbo frame uses the 'RTE_ETHER_MAX_LEN' as boundary condition, but the Ether overhead is larger than 18 when it supports dual VLAN tags. That will cause the jumbo flag rx offload is wrong when MTU size is 'RTE_ETHER_MTU'. This fix will change the boundary condition with 'RTE_ETHER_MTU' and overhead, that perhaps impacts the cases of the jumbo frame related. Fixes: 3151e6a687a3 ("net/octeontx: support MTU") Cc: Harman Kalra Acked-by: Harman Kalra Signed-off-by: Steve Yang --- drivers/net/octeontx/octeontx_ethdev.c | 2 +- drivers/net/octeontx/octeontx_ethdev.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/octeontx/octeontx_ethdev.c b/drivers/net/octeontx/octeontx_ethdev.c index 3ee7b043fd..81779885d5 100644 --- a/drivers/net/octeontx/octeontx_ethdev.c +++ b/drivers/net/octeontx/octeontx_ethdev.c @@ -552,7 +552,7 @@ octeontx_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) if (rc) return rc; - if (frame_size > RTE_ETHER_MAX_LEN) + if (frame_size > OCCTX_L2_MAX_LEN) nic->rx_offloads |= DEV_RX_OFFLOAD_JUMBO_FRAME; else nic->rx_offloads &= ~DEV_RX_OFFLOAD_JUMBO_FRAME; diff --git a/drivers/net/octeontx/octeontx_ethdev.h b/drivers/net/octeontx/octeontx_ethdev.h index 7246fb6d1d..780a094ffa 100644 --- a/drivers/net/octeontx/octeontx_ethdev.h +++ b/drivers/net/octeontx/octeontx_ethdev.h @@ -44,6 +44,7 @@ /* ETH_HLEN+ETH_FCS+2*VLAN_HLEN */ #define OCCTX_L2_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + \ OCCTX_MAX_VTAG_ACT_SIZE) +#define OCCTX_L2_MAX_LEN (RTE_ETHER_MTU + OCCTX_L2_OVERHEAD) /* Since HW FRS includes NPC VTAG insertion space, user has reduced FRS */ #define OCCTX_MAX_FRS \ -- 2.17.1