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From: Saeed Mahameed <saeed@kernel.org>
To: "David S. Miller" <davem@davemloft.net>,
	Jakub Kicinski <kuba@kernel.org>,
	Jason Gunthorpe <jgg@nvidia.com>
Cc: netdev@vger.kernel.org, linux-rdma@vger.kernel.org,
	alexander.duyck@gmail.com, sridhar.samudrala@intel.com,
	edwin.peer@broadcom.com, dsahern@kernel.org,
	kiran.patil@intel.com, jacob.e.keller@intel.com,
	david.m.ertman@intel.com, dan.j.williams@intel.com,
	Parav Pandit <parav@nvidia.com>, Jiri Pirko <jiri@nvidia.com>,
	Vu Pham <vuhuong@nvidia.com>, Saeed Mahameed <saeedm@nvidia.com>
Subject: [net-next V10 02/14] devlink: Introduce PCI SF port flavour and port attribute
Date: Fri, 22 Jan 2021 11:36:46 -0800	[thread overview]
Message-ID: <20210122193658.282884-3-saeed@kernel.org> (raw)
In-Reply-To: <20210122193658.282884-1-saeed@kernel.org>

From: Parav Pandit <parav@nvidia.com>

A PCI sub-function (SF) represents a portion of the device similar
to PCI VF.

In an eswitch, PCI SF may have port which is normally represented
using a representor netdevice.
To have better visibility of eswitch port, its association with SF,
and its representor netdevice, introduce a PCI SF port flavour.

When devlink port flavour is PCI SF, fill up PCI SF attributes of the
port.

Extend port name creation using PCI PF and SF number scheme on best
effort basis, so that vendor drivers can skip defining their own
scheme.
This is done as cApfNSfM, where A, N and M are controller, PCI PF and
PCI SF number respectively.
This is similar to existing naming for PCI PF and PCI VF ports.

An example view of a PCI SF port:

$ devlink port show pci/0000:06:00.0/32768
pci/0000:06:00.0/32768: type eth netdev ens2f0npf0sf88 flavour pcisf controller 0 pfnum 0 sfnum 88 external false splittable false
  function:
    hw_addr 00:00:00:00:88:88 state active opstate attached

$ devlink port show pci/0000:06:00.0/32768 -jp
{
    "port": {
        "pci/0000:06:00.0/32768": {
            "type": "eth",
            "netdev": "ens2f0npf0sf88",
            "flavour": "pcisf",
            "controller": 0,
            "pfnum": 0,
            "sfnum": 88,
            "splittable": false,
            "function": {
                "hw_addr": "00:00:00:00:88:88",
                "state": "active",
                "opstate": "attached"
            }
        }
    }
}

Signed-off-by: Parav Pandit <parav@nvidia.com>
Reviewed-by: Jiri Pirko <jiri@nvidia.com>
Reviewed-by: Vu Pham <vuhuong@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
---
 include/net/devlink.h        | 16 +++++++++++++++
 include/uapi/linux/devlink.h |  5 +++++
 net/core/devlink.c           | 39 ++++++++++++++++++++++++++++++++++++
 3 files changed, 60 insertions(+)

diff --git a/include/net/devlink.h b/include/net/devlink.h
index f466819cc477..dc3bf8000082 100644
--- a/include/net/devlink.h
+++ b/include/net/devlink.h
@@ -93,6 +93,18 @@ struct devlink_port_pci_vf_attrs {
 	u8 external:1;
 };
 
+/**
+ * struct devlink_port_pci_sf_attrs - devlink port's PCI SF attributes
+ * @controller: Associated controller number
+ * @sf: Associated PCI SF for of the PCI PF for this port.
+ * @pf: Associated PCI PF number for this port.
+ */
+struct devlink_port_pci_sf_attrs {
+	u32 controller;
+	u32 sf;
+	u16 pf;
+};
+
 /**
  * struct devlink_port_attrs - devlink port object
  * @flavour: flavour of the port
@@ -103,6 +115,7 @@ struct devlink_port_pci_vf_attrs {
  * @phys: physical port attributes
  * @pci_pf: PCI PF port attributes
  * @pci_vf: PCI VF port attributes
+ * @pci_sf: PCI SF port attributes
  */
 struct devlink_port_attrs {
 	u8 split:1,
@@ -114,6 +127,7 @@ struct devlink_port_attrs {
 		struct devlink_port_phys_attrs phys;
 		struct devlink_port_pci_pf_attrs pci_pf;
 		struct devlink_port_pci_vf_attrs pci_vf;
+		struct devlink_port_pci_sf_attrs pci_sf;
 	};
 };
 
@@ -1404,6 +1418,8 @@ void devlink_port_attrs_pci_pf_set(struct devlink_port *devlink_port, u32 contro
 				   u16 pf, bool external);
 void devlink_port_attrs_pci_vf_set(struct devlink_port *devlink_port, u32 controller,
 				   u16 pf, u16 vf, bool external);
+void devlink_port_attrs_pci_sf_set(struct devlink_port *devlink_port,
+				   u32 controller, u16 pf, u32 sf);
 int devlink_sb_register(struct devlink *devlink, unsigned int sb_index,
 			u32 size, u16 ingress_pools_count,
 			u16 egress_pools_count, u16 ingress_tc_count,
diff --git a/include/uapi/linux/devlink.h b/include/uapi/linux/devlink.h
index cf89c318f2ac..1a241b09a7f8 100644
--- a/include/uapi/linux/devlink.h
+++ b/include/uapi/linux/devlink.h
@@ -200,6 +200,10 @@ enum devlink_port_flavour {
 	DEVLINK_PORT_FLAVOUR_UNUSED, /* Port which exists in the switch, but
 				      * is not used in any way.
 				      */
+	DEVLINK_PORT_FLAVOUR_PCI_SF, /* Represents eswitch port
+				      * for the PCI SF. It is an internal
+				      * port that faces the PCI SF.
+				      */
 };
 
 enum devlink_param_cmode {
@@ -529,6 +533,7 @@ enum devlink_attr {
 	DEVLINK_ATTR_RELOAD_ACTION_INFO,        /* nested */
 	DEVLINK_ATTR_RELOAD_ACTION_STATS,       /* nested */
 
+	DEVLINK_ATTR_PORT_PCI_SF_NUMBER,	/* u32 */
 	/* add new attributes above here, update the policy in devlink.c */
 
 	__DEVLINK_ATTR_MAX,
diff --git a/net/core/devlink.c b/net/core/devlink.c
index c39496311b71..4cbc02fb602d 100644
--- a/net/core/devlink.c
+++ b/net/core/devlink.c
@@ -690,6 +690,15 @@ static int devlink_nl_port_attrs_put(struct sk_buff *msg,
 		if (nla_put_u8(msg, DEVLINK_ATTR_PORT_EXTERNAL, attrs->pci_vf.external))
 			return -EMSGSIZE;
 		break;
+	case DEVLINK_PORT_FLAVOUR_PCI_SF:
+		if (nla_put_u32(msg, DEVLINK_ATTR_PORT_CONTROLLER_NUMBER,
+				attrs->pci_sf.controller) ||
+		    nla_put_u16(msg, DEVLINK_ATTR_PORT_PCI_PF_NUMBER,
+				attrs->pci_sf.pf) ||
+		    nla_put_u32(msg, DEVLINK_ATTR_PORT_PCI_SF_NUMBER,
+				attrs->pci_sf.sf))
+			return -EMSGSIZE;
+		break;
 	case DEVLINK_PORT_FLAVOUR_PHYSICAL:
 	case DEVLINK_PORT_FLAVOUR_CPU:
 	case DEVLINK_PORT_FLAVOUR_DSA:
@@ -8374,6 +8383,32 @@ void devlink_port_attrs_pci_vf_set(struct devlink_port *devlink_port, u32 contro
 }
 EXPORT_SYMBOL_GPL(devlink_port_attrs_pci_vf_set);
 
+/**
+ *	devlink_port_attrs_pci_sf_set - Set PCI SF port attributes
+ *
+ *	@devlink_port: devlink port
+ *	@controller: associated controller number for the devlink port instance
+ *	@pf: associated PF for the devlink port instance
+ *	@sf: associated SF of a PF for the devlink port instance
+ */
+void devlink_port_attrs_pci_sf_set(struct devlink_port *devlink_port, u32 controller,
+				   u16 pf, u32 sf)
+{
+	struct devlink_port_attrs *attrs = &devlink_port->attrs;
+	int ret;
+
+	if (WARN_ON(devlink_port->registered))
+		return;
+	ret = __devlink_port_attrs_set(devlink_port,
+				       DEVLINK_PORT_FLAVOUR_PCI_SF);
+	if (ret)
+		return;
+	attrs->pci_sf.controller = controller;
+	attrs->pci_sf.pf = pf;
+	attrs->pci_sf.sf = sf;
+}
+EXPORT_SYMBOL_GPL(devlink_port_attrs_pci_sf_set);
+
 static int __devlink_port_phys_port_name_get(struct devlink_port *devlink_port,
 					     char *name, size_t len)
 {
@@ -8422,6 +8457,10 @@ static int __devlink_port_phys_port_name_get(struct devlink_port *devlink_port,
 		n = snprintf(name, len, "pf%uvf%u",
 			     attrs->pci_vf.pf, attrs->pci_vf.vf);
 		break;
+	case DEVLINK_PORT_FLAVOUR_PCI_SF:
+		n = snprintf(name, len, "pf%usf%u", attrs->pci_sf.pf,
+			     attrs->pci_sf.sf);
+		break;
 	}
 
 	if (n >= len)
-- 
2.26.2


  parent reply	other threads:[~2021-01-22 23:13 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-22 19:36 [pull request][net-next V10 00/14] Add mlx5 subfunction support Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 01/14] devlink: Prepare code to fill multiple port function attributes Saeed Mahameed
2021-01-29  1:40   ` patchwork-bot+netdevbpf
2021-01-22 19:36 ` Saeed Mahameed [this message]
2021-01-22 19:36 ` [net-next V10 03/14] devlink: Support add and delete devlink port Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 04/14] devlink: Support get and set state of port function Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 05/14] net/mlx5: Introduce vhca state event notifier Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 06/14] net/mlx5: SF, Add auxiliary device support Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 07/14] net/mlx5: SF, Add auxiliary device driver Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 08/14] net/mlx5: E-switch, Prepare eswitch to handle SF vport Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 09/14] net/mlx5: E-switch, Add eswitch helpers for " Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 10/14] net/mlx5: SF, Add port add delete functionality Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 11/14] net/mlx5: SF, Port function state change support Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 12/14] devlink: Add devlink port documentation Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 13/14] devlink: Extend devlink port documentation for subfunctions Saeed Mahameed
2021-01-22 19:36 ` [net-next V10 14/14] net/mlx5: Add devlink subfunction port documentation Saeed Mahameed
2021-01-24 20:47 ` [pull request][net-next V10 00/14] Add mlx5 subfunction support Edwin Peer
2021-01-25 10:57   ` Parav Pandit
2021-01-25 13:22     ` Jason Gunthorpe
2021-01-25 19:23       ` Edwin Peer
2021-01-25 19:49         ` Jason Gunthorpe
2021-01-25 20:05           ` Edwin Peer
2021-01-25 20:22             ` Michael Chan
2021-01-25 20:26             ` Parav Pandit
2021-01-25 18:35     ` Edwin Peer
2021-01-25 19:34       ` Edwin Peer
2021-01-25 19:59         ` Jason Gunthorpe
2021-01-25 20:22           ` Edwin Peer
2021-01-25 20:41             ` Jason Gunthorpe
2021-01-25 21:23               ` Edwin Peer
2021-01-25 23:13                 ` Jason Gunthorpe
2021-01-27  1:34 ` Jakub Kicinski
2021-01-29  0:03   ` Saeed Mahameed
2021-01-29  0:11     ` Jakub Kicinski

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