From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 667FDC433DB for ; Tue, 2 Feb 2021 15:45:41 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2689964F65 for ; Tue, 2 Feb 2021 15:45:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235556AbhBBPpf (ORCPT ); Tue, 2 Feb 2021 10:45:35 -0500 Received: from mga01.intel.com ([192.55.52.88]:38091 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232613AbhBBPnx (ORCPT ); Tue, 2 Feb 2021 10:43:53 -0500 IronPort-SDR: IUKrkkgKImNg9a7JSRh4Of3l3RP65cQ8cWe6jhe0hgzomQzUJeEwgkAQMnLtbKVfxcLO4TWgcj T7NuJGvatPug== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="199795408" X-IronPort-AV: E=Sophos;i="5.79,395,1602572400"; d="scan'208";a="199795408" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2021 07:43:00 -0800 IronPort-SDR: M3sxghbhCUXV3lOt/rjkR7vQzdR0bVxR0CqkNCARA3Jj+UKTnk7tZNYKBMMJ6EknXm9MjkQpC5 hLL3EwMqtrog== X-IronPort-AV: E=Sophos;i="5.79,395,1602572400"; d="scan'208";a="391527749" Received: from joship1x-mobl1.amr.corp.intel.com (HELO intel.com) ([10.252.131.202]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2021 07:42:58 -0800 Date: Tue, 2 Feb 2021 07:42:57 -0800 From: Ben Widawsky To: "Michael S. Tsirkin" Cc: Jonathan Cameron , qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, Chris Browy , Dan Williams , David Hildenbrand , Igor Mammedov , Ira Weiny , Marcel Apfelbaum , Markus Armbruster , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Vishal Verma , "John Groves (jgroves)" Subject: Re: [RFC PATCH v3 16/31] hw/pci: Plumb _UID through host bridges Message-ID: <20210202154257.zepdz74logmi52wn@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> <20210202005948.241655-17-ben.widawsky@intel.com> <20210202150056.00003bec@Huawei.com> <20210202101504-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210202101504-mutt-send-email-mst@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Thanks for looking! Mixing comments to Jonathan and Michael.. On 21-02-02 10:24:43, Michael S. Tsirkin wrote: > On Tue, Feb 02, 2021 at 03:00:56PM +0000, Jonathan Cameron wrote: > > On Mon, 1 Feb 2021 16:59:33 -0800 > > Ben Widawsky wrote: > > > > > Currently, QEMU makes _UID equivalent to the bus number (_BBN). While > > > there is nothing wrong with doing it this way, CXL spec has a heavy > > > reliance on _UID to identify host bridges and there is no link to the > > > bus number. Having a distinct UID solves two problems. The first is it > > > gets us around the limitation of 256 (current max bus number). > > Not sure I understand. You want more than 256 host bridges? > I don't want more than 256 host bridges, but I want the ability to disaggregate _UID and bus (_BBN). The reasoning is just to align with the spec where _UID is used to identify a CXL host bridge which is unrelated (perhaps) to the bus number. > > The > > > second is it allows us to replicate hardware configurations where bus > > > number and uid aren't equivalent. > > A bit more data on when this needs to be the case? > Doesn't *need* to be the case. I was making a concerted effort to allow full spec flexibility, but I don't believe it to be necessary unless we want to accurately emulate a real platform. > > The latter has benefits for our > > > development and debugging using QEMU. > > > > > > The other way to do this would be to implement the expanded bus > > > numbering, but having an explicit uid makes more sense when trying to > > > replicate real hardware configurations. > > > > > > The QEMU commandline to utilize this would be: > > > -device pxb-cxl,id=cxl.0,bus="pcie.0",bus_nr=1,uid=x > > > > > > Signed-off-by: Ben Widawsky > > However, if doing this how do we ensure UID is still unique? > What do we do for cases where UID was not specified? > One idea is to generate a string UID and just stick the bus # > in there. This is totally mishandled in the code currently. I like your idea though. > > > > > -- > > > > > > I'm guessing this patch will be somewhat controversial. For early CXL > > > work, this can be dropped without too much heartache. > > > > Whilst I'm not personally against, this maybe best to drop for now as you > > say. > > I think it'd be good to understand from the PCIe experts if CXL matches in this regard. If PCIe generally allows (and does in practice) _UID not matching _BBN, perhaps this is an overall improvement to the code. > > > --- > > > hw/i386/acpi-build.c | 3 ++- > > > hw/pci-bridge/pci_expander_bridge.c | 19 +++++++++++++++++++ > > > hw/pci/pci.c | 11 +++++++++++ > > > include/hw/pci/pci.h | 1 + > > > include/hw/pci/pci_bus.h | 1 + > > > 5 files changed, 34 insertions(+), 1 deletion(-) > > > > > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > > > index cf6eb54c22..145a503e92 100644 > > > --- a/hw/i386/acpi-build.c > > > +++ b/hw/i386/acpi-build.c > > > @@ -1343,6 +1343,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > > QLIST_FOREACH(bus, &bus->child, sibling) { > > > uint8_t bus_num = pci_bus_num(bus); > > > uint8_t numa_node = pci_bus_numa_node(bus); > > > + int32_t uid = pci_bus_uid(bus); > > > > > > /* look only for expander root buses */ > > > if (!pci_bus_is_root(bus)) { > > > @@ -1356,7 +1357,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > > scope = aml_scope("\\_SB"); > > > dev = aml_device("PC%.02X", bus_num); > > > aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); > > > - init_pci_acpi(dev, bus_num, pci_bus_is_express(bus) ? PCIE : PCI); > > > + init_pci_acpi(dev, uid, pci_bus_is_express(bus) ? PCIE : PCI); > > > > > > if (numa_node != NUMA_NODE_UNASSIGNED) { > > > aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); > > > diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c > > > index b42592e1ff..5021b60435 100644 > > > --- a/hw/pci-bridge/pci_expander_bridge.c > > > +++ b/hw/pci-bridge/pci_expander_bridge.c > > > @@ -67,6 +67,7 @@ struct PXBDev { > > > > > > uint8_t bus_nr; > > > uint16_t numa_node; > > > + int32_t uid; > > > }; > > > > > > static PXBDev *convert_to_pxb(PCIDevice *dev) > > As long as we are doing this, do we want to support a string uid too? > How about a 64 bit uid? Why not? If generally the idea of the patch is welcome, I am happy to change it. > > > > > @@ -98,12 +99,20 @@ static uint16_t pxb_bus_numa_node(PCIBus *bus) > > > return pxb->numa_node; > > > } > > > > > > +static int32_t pxb_bus_uid(PCIBus *bus) > > > +{ > > > + PXBDev *pxb = convert_to_pxb(bus->parent_dev); > > > + > > > + return pxb->uid; > > > +} > > > + > > > static void pxb_bus_class_init(ObjectClass *class, void *data) > > > { > > > PCIBusClass *pbc = PCI_BUS_CLASS(class); > > > > > > pbc->bus_num = pxb_bus_num; > > > pbc->numa_node = pxb_bus_numa_node; > > > + pbc->uid = pxb_bus_uid; > > > } > > > > > > static const TypeInfo pxb_bus_info = { > > > @@ -329,6 +338,7 @@ static Property pxb_dev_properties[] = { > > > /* Note: 0 is not a legal PXB bus number. */ > > > DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0), > > > DEFINE_PROP_UINT16("numa_node", PXBDev, numa_node, NUMA_NODE_UNASSIGNED), > > > + DEFINE_PROP_INT32("uid", PXBDev, uid, -1), > > > DEFINE_PROP_END_OF_LIST(), > > > }; > > > > > > @@ -400,12 +410,21 @@ static const TypeInfo pxb_pcie_dev_info = { > > > > > > static void pxb_cxl_dev_realize(PCIDevice *dev, Error **errp) > > > { > > > + PXBDev *pxb = convert_to_pxb(dev); > > > + > > > /* A CXL PXB's parent bus is still PCIe */ > > > if (!pci_bus_is_express(pci_get_bus(dev))) { > > > error_setg(errp, "pxb-cxl devices cannot reside on a PCI bus"); > > > return; > > > } > > > > > > + if (pxb->uid < 0) { > > > + error_setg(errp, "pxb-cxl devices must have a valid uid (0-2147483647)"); > > > + return; > > > + } > > > + > > > + /* FIXME: Check that uid doesn't collide with UIDs of other host bridges */ > > > + > > > pxb_dev_realize_common(dev, CXL, errp); > > > } > > > > > > diff --git a/hw/pci/pci.c b/hw/pci/pci.c > > > index adbe8aa260..bf019d91a0 100644 > > > --- a/hw/pci/pci.c > > > +++ b/hw/pci/pci.c > > > @@ -170,6 +170,11 @@ static uint16_t pcibus_numa_node(PCIBus *bus) > > > return NUMA_NODE_UNASSIGNED; > > > } > > > > > > +static int32_t pcibus_uid(PCIBus *bus) > > > +{ > > > + return -1; > > > +} > > > + > > > static void pci_bus_class_init(ObjectClass *klass, void *data) > > > { > > > BusClass *k = BUS_CLASS(klass); > > > @@ -184,6 +189,7 @@ static void pci_bus_class_init(ObjectClass *klass, void *data) > > > > > > pbc->bus_num = pcibus_num; > > > pbc->numa_node = pcibus_numa_node; > > > + pbc->uid = pcibus_uid; > > > } > > > > > > static const TypeInfo pci_bus_info = { > > > @@ -530,6 +536,11 @@ int pci_bus_numa_node(PCIBus *bus) > > > return PCI_BUS_GET_CLASS(bus)->numa_node(bus); > > > } > > > > > > +int pci_bus_uid(PCIBus *bus) > > > +{ > > > + return PCI_BUS_GET_CLASS(bus)->uid(bus); > > > +} > > > + > > > static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, > > > const VMStateField *field) > > > { > > > diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h > > > index bde3697bee..a46de48ccd 100644 > > > --- a/include/hw/pci/pci.h > > > +++ b/include/hw/pci/pci.h > > > @@ -463,6 +463,7 @@ static inline int pci_dev_bus_num(const PCIDevice *dev) > > > } > > > > > > int pci_bus_numa_node(PCIBus *bus); > > > +int pci_bus_uid(PCIBus *bus); > > > void pci_for_each_device(PCIBus *bus, int bus_num, > > > void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), > > > void *opaque); > > > diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h > > > index eb94e7e85c..3c9fbc55bb 100644 > > > --- a/include/hw/pci/pci_bus.h > > > +++ b/include/hw/pci/pci_bus.h > > > @@ -17,6 +17,7 @@ struct PCIBusClass { > > > > > > int (*bus_num)(PCIBus *bus); > > > uint16_t (*numa_node)(PCIBus *bus); > > > + int32_t (*uid)(PCIBus *bus); > > > }; > > > > > > enum PCIBusFlags { > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53CE6C433DB for ; Tue, 2 Feb 2021 16:07:36 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D49B164F69 for ; Tue, 2 Feb 2021 16:07:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D49B164F69 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:50752 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l6yDG-0001ZF-P1 for qemu-devel@archiver.kernel.org; Tue, 02 Feb 2021 11:07:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38250) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6xpi-00018P-7E for qemu-devel@nongnu.org; Tue, 02 Feb 2021 10:43:14 -0500 Received: from mga04.intel.com ([192.55.52.120]:42343) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l6xpe-00043a-VI for qemu-devel@nongnu.org; Tue, 02 Feb 2021 10:43:13 -0500 IronPort-SDR: plJjAZAoMihVtuNjVg9Tlbt8WFJyN39iwT2icsRqTV5mSdG0T0cZ5qORKykIfTEG7gPv0m9n2x zA0mHMKOHgpQ== X-IronPort-AV: E=McAfee;i="6000,8403,9882"; a="178313366" X-IronPort-AV: E=Sophos;i="5.79,395,1602572400"; d="scan'208";a="178313366" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2021 07:43:00 -0800 IronPort-SDR: M3sxghbhCUXV3lOt/rjkR7vQzdR0bVxR0CqkNCARA3Jj+UKTnk7tZNYKBMMJ6EknXm9MjkQpC5 hLL3EwMqtrog== X-IronPort-AV: E=Sophos;i="5.79,395,1602572400"; d="scan'208";a="391527749" Received: from joship1x-mobl1.amr.corp.intel.com (HELO intel.com) ([10.252.131.202]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Feb 2021 07:42:58 -0800 Date: Tue, 2 Feb 2021 07:42:57 -0800 From: Ben Widawsky To: "Michael S. Tsirkin" Subject: Re: [RFC PATCH v3 16/31] hw/pci: Plumb _UID through host bridges Message-ID: <20210202154257.zepdz74logmi52wn@intel.com> References: <20210202005948.241655-1-ben.widawsky@intel.com> <20210202005948.241655-17-ben.widawsky@intel.com> <20210202150056.00003bec@Huawei.com> <20210202101504-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210202101504-mutt-send-email-mst@kernel.org> Received-SPF: pass client-ip=192.55.52.120; envelope-from=ben.widawsky@intel.com; helo=mga04.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Hildenbrand , Vishal Verma , "John Groves \(jgroves\)" , Chris Browy , qemu-devel@nongnu.org, linux-cxl@vger.kernel.org, Markus Armbruster , Jonathan Cameron , Igor Mammedov , Dan Williams , Ira Weiny , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Thanks for looking! Mixing comments to Jonathan and Michael.. On 21-02-02 10:24:43, Michael S. Tsirkin wrote: > On Tue, Feb 02, 2021 at 03:00:56PM +0000, Jonathan Cameron wrote: > > On Mon, 1 Feb 2021 16:59:33 -0800 > > Ben Widawsky wrote: > > > > > Currently, QEMU makes _UID equivalent to the bus number (_BBN). While > > > there is nothing wrong with doing it this way, CXL spec has a heavy > > > reliance on _UID to identify host bridges and there is no link to the > > > bus number. Having a distinct UID solves two problems. The first is it > > > gets us around the limitation of 256 (current max bus number). > > Not sure I understand. You want more than 256 host bridges? > I don't want more than 256 host bridges, but I want the ability to disaggregate _UID and bus (_BBN). The reasoning is just to align with the spec where _UID is used to identify a CXL host bridge which is unrelated (perhaps) to the bus number. > > The > > > second is it allows us to replicate hardware configurations where bus > > > number and uid aren't equivalent. > > A bit more data on when this needs to be the case? > Doesn't *need* to be the case. I was making a concerted effort to allow full spec flexibility, but I don't believe it to be necessary unless we want to accurately emulate a real platform. > > The latter has benefits for our > > > development and debugging using QEMU. > > > > > > The other way to do this would be to implement the expanded bus > > > numbering, but having an explicit uid makes more sense when trying to > > > replicate real hardware configurations. > > > > > > The QEMU commandline to utilize this would be: > > > -device pxb-cxl,id=cxl.0,bus="pcie.0",bus_nr=1,uid=x > > > > > > Signed-off-by: Ben Widawsky > > However, if doing this how do we ensure UID is still unique? > What do we do for cases where UID was not specified? > One idea is to generate a string UID and just stick the bus # > in there. This is totally mishandled in the code currently. I like your idea though. > > > > > -- > > > > > > I'm guessing this patch will be somewhat controversial. For early CXL > > > work, this can be dropped without too much heartache. > > > > Whilst I'm not personally against, this maybe best to drop for now as you > > say. > > I think it'd be good to understand from the PCIe experts if CXL matches in this regard. If PCIe generally allows (and does in practice) _UID not matching _BBN, perhaps this is an overall improvement to the code. > > > --- > > > hw/i386/acpi-build.c | 3 ++- > > > hw/pci-bridge/pci_expander_bridge.c | 19 +++++++++++++++++++ > > > hw/pci/pci.c | 11 +++++++++++ > > > include/hw/pci/pci.h | 1 + > > > include/hw/pci/pci_bus.h | 1 + > > > 5 files changed, 34 insertions(+), 1 deletion(-) > > > > > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > > > index cf6eb54c22..145a503e92 100644 > > > --- a/hw/i386/acpi-build.c > > > +++ b/hw/i386/acpi-build.c > > > @@ -1343,6 +1343,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > > QLIST_FOREACH(bus, &bus->child, sibling) { > > > uint8_t bus_num = pci_bus_num(bus); > > > uint8_t numa_node = pci_bus_numa_node(bus); > > > + int32_t uid = pci_bus_uid(bus); > > > > > > /* look only for expander root buses */ > > > if (!pci_bus_is_root(bus)) { > > > @@ -1356,7 +1357,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > > scope = aml_scope("\\_SB"); > > > dev = aml_device("PC%.02X", bus_num); > > > aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); > > > - init_pci_acpi(dev, bus_num, pci_bus_is_express(bus) ? PCIE : PCI); > > > + init_pci_acpi(dev, uid, pci_bus_is_express(bus) ? PCIE : PCI); > > > > > > if (numa_node != NUMA_NODE_UNASSIGNED) { > > > aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); > > > diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c > > > index b42592e1ff..5021b60435 100644 > > > --- a/hw/pci-bridge/pci_expander_bridge.c > > > +++ b/hw/pci-bridge/pci_expander_bridge.c > > > @@ -67,6 +67,7 @@ struct PXBDev { > > > > > > uint8_t bus_nr; > > > uint16_t numa_node; > > > + int32_t uid; > > > }; > > > > > > static PXBDev *convert_to_pxb(PCIDevice *dev) > > As long as we are doing this, do we want to support a string uid too? > How about a 64 bit uid? Why not? If generally the idea of the patch is welcome, I am happy to change it. > > > > > @@ -98,12 +99,20 @@ static uint16_t pxb_bus_numa_node(PCIBus *bus) > > > return pxb->numa_node; > > > } > > > > > > +static int32_t pxb_bus_uid(PCIBus *bus) > > > +{ > > > + PXBDev *pxb = convert_to_pxb(bus->parent_dev); > > > + > > > + return pxb->uid; > > > +} > > > + > > > static void pxb_bus_class_init(ObjectClass *class, void *data) > > > { > > > PCIBusClass *pbc = PCI_BUS_CLASS(class); > > > > > > pbc->bus_num = pxb_bus_num; > > > pbc->numa_node = pxb_bus_numa_node; > > > + pbc->uid = pxb_bus_uid; > > > } > > > > > > static const TypeInfo pxb_bus_info = { > > > @@ -329,6 +338,7 @@ static Property pxb_dev_properties[] = { > > > /* Note: 0 is not a legal PXB bus number. */ > > > DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0), > > > DEFINE_PROP_UINT16("numa_node", PXBDev, numa_node, NUMA_NODE_UNASSIGNED), > > > + DEFINE_PROP_INT32("uid", PXBDev, uid, -1), > > > DEFINE_PROP_END_OF_LIST(), > > > }; > > > > > > @@ -400,12 +410,21 @@ static const TypeInfo pxb_pcie_dev_info = { > > > > > > static void pxb_cxl_dev_realize(PCIDevice *dev, Error **errp) > > > { > > > + PXBDev *pxb = convert_to_pxb(dev); > > > + > > > /* A CXL PXB's parent bus is still PCIe */ > > > if (!pci_bus_is_express(pci_get_bus(dev))) { > > > error_setg(errp, "pxb-cxl devices cannot reside on a PCI bus"); > > > return; > > > } > > > > > > + if (pxb->uid < 0) { > > > + error_setg(errp, "pxb-cxl devices must have a valid uid (0-2147483647)"); > > > + return; > > > + } > > > + > > > + /* FIXME: Check that uid doesn't collide with UIDs of other host bridges */ > > > + > > > pxb_dev_realize_common(dev, CXL, errp); > > > } > > > > > > diff --git a/hw/pci/pci.c b/hw/pci/pci.c > > > index adbe8aa260..bf019d91a0 100644 > > > --- a/hw/pci/pci.c > > > +++ b/hw/pci/pci.c > > > @@ -170,6 +170,11 @@ static uint16_t pcibus_numa_node(PCIBus *bus) > > > return NUMA_NODE_UNASSIGNED; > > > } > > > > > > +static int32_t pcibus_uid(PCIBus *bus) > > > +{ > > > + return -1; > > > +} > > > + > > > static void pci_bus_class_init(ObjectClass *klass, void *data) > > > { > > > BusClass *k = BUS_CLASS(klass); > > > @@ -184,6 +189,7 @@ static void pci_bus_class_init(ObjectClass *klass, void *data) > > > > > > pbc->bus_num = pcibus_num; > > > pbc->numa_node = pcibus_numa_node; > > > + pbc->uid = pcibus_uid; > > > } > > > > > > static const TypeInfo pci_bus_info = { > > > @@ -530,6 +536,11 @@ int pci_bus_numa_node(PCIBus *bus) > > > return PCI_BUS_GET_CLASS(bus)->numa_node(bus); > > > } > > > > > > +int pci_bus_uid(PCIBus *bus) > > > +{ > > > + return PCI_BUS_GET_CLASS(bus)->uid(bus); > > > +} > > > + > > > static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, > > > const VMStateField *field) > > > { > > > diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h > > > index bde3697bee..a46de48ccd 100644 > > > --- a/include/hw/pci/pci.h > > > +++ b/include/hw/pci/pci.h > > > @@ -463,6 +463,7 @@ static inline int pci_dev_bus_num(const PCIDevice *dev) > > > } > > > > > > int pci_bus_numa_node(PCIBus *bus); > > > +int pci_bus_uid(PCIBus *bus); > > > void pci_for_each_device(PCIBus *bus, int bus_num, > > > void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque), > > > void *opaque); > > > diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h > > > index eb94e7e85c..3c9fbc55bb 100644 > > > --- a/include/hw/pci/pci_bus.h > > > +++ b/include/hw/pci/pci_bus.h > > > @@ -17,6 +17,7 @@ struct PCIBusClass { > > > > > > int (*bus_num)(PCIBus *bus); > > > uint16_t (*numa_node)(PCIBus *bus); > > > + int32_t (*uid)(PCIBus *bus); > > > }; > > > > > > enum PCIBusFlags { >