[PATCH 10/16] ppc: Remove MPC8544DS board

[Tom Rini <trini@konsulko.com>]

This board relies on using CONFIG_LIBATA but does not enable CONFIG_AHCI.  The
deadline for this conversion was the v2019.07 release.  The use of CONFIG_AHCI
requires CONFIG_DM.  The deadline for this conversion was v2020.01.  Remove
this board.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
---
 arch/powerpc/cpu/mpc85xx/Kconfig      |   6 -
 board/freescale/mpc8544ds/Kconfig     |  12 -
 board/freescale/mpc8544ds/MAINTAINERS |   6 -
 board/freescale/mpc8544ds/Makefile    |  10 -
 board/freescale/mpc8544ds/README      | 122 --------
 board/freescale/mpc8544ds/ddr.c       |  56 ----
 board/freescale/mpc8544ds/law.c       |  17 --
 board/freescale/mpc8544ds/mpc8544ds.c | 321 --------------------
 board/freescale/mpc8544ds/tlb.c       |  74 -----
 configs/MPC8544DS_defconfig           |  52 ----
 include/configs/MPC8544DS.h           | 408 --------------------------
 11 files changed, 1084 deletions(-)
 delete mode 100644 board/freescale/mpc8544ds/Kconfig
 delete mode 100644 board/freescale/mpc8544ds/MAINTAINERS
 delete mode 100644 board/freescale/mpc8544ds/Makefile
 delete mode 100644 board/freescale/mpc8544ds/README
 delete mode 100644 board/freescale/mpc8544ds/ddr.c
 delete mode 100644 board/freescale/mpc8544ds/law.c
 delete mode 100644 board/freescale/mpc8544ds/mpc8544ds.c
 delete mode 100644 board/freescale/mpc8544ds/tlb.c
 delete mode 100644 configs/MPC8544DS_defconfig
 delete mode 100644 include/configs/MPC8544DS.h

diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index c1a377067106..28c9f113d3f5 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -52,11 +52,6 @@ config TARGET_MPC8541CDS
 	bool "Support MPC8541CDS"
 	select ARCH_MPC8541
 
-config TARGET_MPC8544DS
-	bool "Support MPC8544DS"
-	select ARCH_MPC8544
-	imply PANIC_HANG
-
 config TARGET_MPC8548CDS
 	bool "Support MPC8548CDS"
 	select ARCH_MPC8548
@@ -1443,7 +1438,6 @@ config SYS_FSL_LBC_CLK_DIV
 
 source "board/freescale/corenet_ds/Kconfig"
 source "board/freescale/mpc8541cds/Kconfig"
-source "board/freescale/mpc8544ds/Kconfig"
 source "board/freescale/mpc8548cds/Kconfig"
 source "board/freescale/mpc8555cds/Kconfig"
 source "board/freescale/mpc8568mds/Kconfig"
diff --git a/board/freescale/mpc8544ds/Kconfig b/board/freescale/mpc8544ds/Kconfig
deleted file mode 100644
index c3e25b89a028..000000000000
--- a/board/freescale/mpc8544ds/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_MPC8544DS
-
-config SYS_BOARD
-	default "mpc8544ds"
-
-config SYS_VENDOR
-	default "freescale"
-
-config SYS_CONFIG_NAME
-	default "MPC8544DS"
-
-endif
diff --git a/board/freescale/mpc8544ds/MAINTAINERS b/board/freescale/mpc8544ds/MAINTAINERS
deleted file mode 100644
index 74e7249e4734..000000000000
--- a/board/freescale/mpc8544ds/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MPC8544DS BOARD
-M:	Priyanka Jain <priyanka.jain@nxp.com>
-S:	Maintained
-F:	board/freescale/mpc8544ds/
-F:	include/configs/MPC8544DS.h
-F:	configs/MPC8544DS_defconfig
diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile
deleted file mode 100644
index 1693ae84330e..000000000000
--- a/board/freescale/mpc8544ds/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright 2007 Freescale Semiconductor, Inc.
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-
-obj-y	+= mpc8544ds.o
-obj-y	+= ddr.o
-obj-y	+= law.o
-obj-y	+= tlb.o
diff --git a/board/freescale/mpc8544ds/README b/board/freescale/mpc8544ds/README
deleted file mode 100644
index b49c3c07c405..000000000000
--- a/board/freescale/mpc8544ds/README
+++ /dev/null
@@ -1,122 +0,0 @@
-Overview
---------
-The MPC8544DS system is similar to the 85xx CDS systems such
-as the MPC8548CDS due to the similar E500 core.  However, it
-is placed on the same board as the 8641 HPCN system.
-
-
-Flash Banks
------------
-Like the 85xx CDS systems, the 8544 DS board has two flash banks.
-They are both present on boot, but there locations can be swapped
-using the dip-switch SW10, bit 2.
-
-However, unlike the CDS systems, but similar to the 8641 HPCN
-board, a runtime reset through the FPGA can also affect a swap
-on the flash bank mappings for the next reset cycle.
-
-Irrespective of the switch SW10[2], booting is always from the
-boot bank at 0xfff8_0000.
-
-
-Memory Map
-----------
-
-0xff80_0000 - 0xffbf_ffff	Alternate bank		4MB
-0xffc0_0000 - 0xffff_ffff	Boot bank		4MB
-
-0xffb8_0000			Alternate image start	512KB
-0xfff8_0000			Boot image start	512KB
-
-
-Flashing Images
----------------
-
-For example, to place a new image in the alternate flash bank
-and then reset with that new image temporarily, use this:
-
-    tftp 1000000 u-boot.bin.8544ds
-    erase ffb80000 ffbfffff
-    cp.b 1000000 ffb80000 80000
-    pixis_reset altbank
-
-
-To overwrite the image in the boot flash bank:
-
-    tftp 1000000 u-boot.bin.8544ds
-    protect off all
-    erase fff80000 ffffffff
-    cp.b 1000000 fff80000 80000
-
-Other example U-Boot image and flash manipulations examples
-can be found in the README.mpc85xxcds file as well.
-
-
-The pixis_reset command
------------------------
-A new command, "pixis_reset", is introduced to reset mpc8641hpcn board
-using the FPGA sequencer.  When the board restarts, it has the option
-of using either the current or alternate flash bank as the boot
-image, with or without the watchdog timer enabled, and finally with
-or without frequency changes.
-
-Usage is;
-
-	pixis_reset
-	pixis_reset altbank
-	pixis_reset altbank wd
-	pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-	pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>
-
-Examples;
-
-	/* reset to current bank, like "reset" command */
-	pixis_reset
-
-	/* reset board but use the to alternate flash bank */
-	pixis_reset altbank
-
-	/* reset board, use alternate flash bank with watchdog timer enabled*/
-	pixis_reset altbank wd
-
-	/* reset board to alternate bank with frequency changed.
-	 * 40 is SYSCLK, 2.5 is COREPLL ratio, 10 is MPXPLL ratio
-	 */
-	pixis-reset altbank cf 40 2.5 10
-
-Valid clock choices are in the 8641 Reference Manuals.
-
-
-Using the Device Tree Source File
----------------------------------
-To create the DTB (Device Tree Binary) image file,
-use a command similar to this:
-
-    dtc -b 0 -f -I dts -O dtb mpc8544ds.dts > mpc8544ds.dtb
-
-Likely, that .dts file will come from here;
-
-    linux-2.6/arch/powerpc/boot/dts/mpc8544ds.dts
-
-After placing the DTB file in your TFTP disk area,
-you can download that dtb file using a command like:
-
-    tftp 900000 mpc8544ds.dtb
-
-Burn it to flash if you want.
-
-
-Booting Linux
--------------
-
-Place a linux uImage in the TFTP disk area too.
-
-    tftp 1000000 uImage.8544
-    tftp 900000 mpc8544ds.dtb
-    bootm 1000000 - 900000
-
-Watch your ethact, netdev and bootargs U-Boot environment variables.
-You may want to do something like this too:
-
-    setenv ethact eTSEC3
-    setenv netdev eth1
diff --git a/board/freescale/mpc8544ds/ddr.c b/board/freescale/mpc8544ds/ddr.c
deleted file mode 100644
index c4d985347b3f..000000000000
--- a/board/freescale/mpc8544ds/ddr.c
+++ /dev/null
@@ -1,56 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-
-#include <fsl_ddr_sdram.h>
-#include <fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
-				dimm_params_t *pdimm,
-				unsigned int ctrl_num)
-{
-	/*
-	 * Factors to consider for clock adjust:
-	 *	- number of chips on bus
-	 *	- position of slot
-	 *	- DDR1 vs. DDR2?
-	 *	- ???
-	 *
-	 * This needs to be determined on a board-by-board basis.
-	 *	0110	3/4 cycle late
-	 *	0111	7/8 cycle late
-	 */
-	popts->clk_adjust = 7;
-
-	/*
-	 * Factors to consider for CPO:
-	 *	- frequency
-	 *	- ddr1 vs. ddr2
-	 */
-	popts->cpo_override = 10;
-
-	/*
-	 * Factors to consider for write data delay:
-	 *	- number of DIMMs
-	 *
-	 * 1 = 1/4 clock delay
-	 * 2 = 1/2 clock delay
-	 * 3 = 3/4 clock delay
-	 * 4 = 1   clock delay
-	 * 5 = 5/4 clock delay
-	 * 6 = 3/2 clock delay
-	 */
-	popts->write_data_delay = 3;
-
-	/* 2T timing enable */
-	popts->twot_en = 1;
-
-	/*
-	 * Factors to consider for half-strength driver enable:
-	 *	- number of DIMMs installed
-	 */
-	popts->half_strength_driver_enable = 0;
-}
diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c
deleted file mode 100644
index 52cec7fbb598..000000000000
--- a/board/freescale/mpc8544ds/law.c
+++ /dev/null
@@ -1,17 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008, 2010 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
deleted file mode 100644
index 30ed7083657f..000000000000
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ /dev/null
@@ -1,321 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <net.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_serdes.h>
-#include <asm/io.h>
-#include <miiphy.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <fsl_mdio.h>
-#include <tsec.h>
-#include <netdev.h>
-
-#include "../common/sgmii_riser.h"
-
-int checkboard (void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
-	u8 vboot;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	if ((uint)&gur->porpllsr != 0xe00e0000) {
-		printf("immap size error %lx\n",(ulong)&gur->porpllsr);
-	}
-	printf ("Board: MPC8544DS, Sys ID: 0x%02x, "
-		"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
-		in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
-		in_8(pixis_base + PIXIS_PVER));
-
-	vboot = in_8(pixis_base + PIXIS_VBOOT);
-	if (vboot & PIXIS_VBOOT_FMAP)
-		printf ("vBank: %d\n", ((vboot & PIXIS_VBOOT_FBANK) >> 6));
-	else
-		puts ("Promjet\n");
-
-	lbc->ltesr = 0xffffffff;	/* Clear LBC error interrupts */
-	lbc->lteir = 0xffffffff;	/* Enable LBC error interrupts */
-	ecm->eedr = 0xffffffff;		/* Clear ecm errors */
-	ecm->eeer = 0xffffffff;		/* Enable ecm errors */
-
-	return 0;
-}
-
-#ifdef CONFIG_PCI1
-static struct pci_controller pci1_hose;
-#endif
-
-#ifdef CONFIG_PCIE3
-static struct pci_controller pcie3_hose;
-#endif
-
-void pci_init_board(void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct fsl_pci_info pci_info;
-	u32 devdisr, pordevsr, io_sel;
-	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
-	int first_free_busno = 0;
-
-	int pcie_ep, pcie_configured;
-
-	devdisr = in_be32(&gur->devdisr);
-	pordevsr = in_be32(&gur->pordevsr);
-	porpllsr = in_be32(&gur->porpllsr);
-	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-
-	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
-
-	puts("\n");
-
-#ifdef CONFIG_PCIE3
-	pcie_configured = is_serdes_configured(PCIE3);
-
-	if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
-		/* contains both PCIE3 MEM & IO space */
-		set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M,
-				LAW_TRGT_IF_PCIE_3);
-		SET_STD_PCIE_INFO(pci_info, 3);
-		pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info.regs);
-
-		/* outbound memory */
-		pci_set_region(&pcie3_hose.regions[0],
-			       CONFIG_SYS_PCIE3_MEM_BUS2,
-			       CONFIG_SYS_PCIE3_MEM_PHYS2,
-			       CONFIG_SYS_PCIE3_MEM_SIZE2,
-			       PCI_REGION_MEM);
-
-		pcie3_hose.region_count = 1;
-
-		printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
-			pcie_ep ? "Endpoint" : "Root Complex",
-			pci_info.regs);
-		first_free_busno = fsl_pci_init_port(&pci_info,
-					&pcie3_hose, first_free_busno);
-
-		/*
-		 * Activate ULI1575 legacy chip by performing a fake
-		 * memory access.  Needed to make ULI RTC work.
-		 */
-		in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
-	} else {
-		printf("PCIE3: disabled\n");
-	}
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE1
-	SET_STD_PCIE_INFO(pci_info, 1);
-	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE1, &pci_info);
-#else
-	setbits_be32(&gur->devdisr, _DEVDISR_PCIE1); /* disable */
-#endif
-
-#ifdef CONFIG_PCIE2
-	SET_STD_PCIE_INFO(pci_info, 2);
-	first_free_busno = fsl_pcie_init_ctrl(first_free_busno, devdisr, PCIE2, &pci_info);
-#else
-	setbits_be32(&gur->devdisr, _DEVDISR_PCIE2); /* disable */
-#endif
-
-#ifdef CONFIG_PCI1
-	pci_speed = 66666000;
-	pci_32 = 1;
-	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
-	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
-
-	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info, 1);
-		set_next_law(pci_info.mem_phys,
-			law_size_bits(pci_info.mem_size), pci_info.law);
-		set_next_law(pci_info.io_phys,
-			law_size_bits(pci_info.io_size), pci_info.law);
-
-		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
-		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
-			(pci_32) ? 32 : 64,
-			(pci_speed == 33333000) ? "33" :
-			(pci_speed == 66666000) ? "66" : "unknown",
-			pci_clk_sel ? "sync" : "async",
-			pci_agent ? "agent" : "host",
-			pci_arb ? "arbiter" : "external-arbiter",
-			pci_info.regs);
-
-		first_free_busno = fsl_pci_init_port(&pci_info,
-					&pci1_hose, first_free_busno);
-	} else {
-		printf("PCI: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
-#endif
-}
-
-int last_stage_init(void)
-{
-	return 0;
-}
-
-
-unsigned long
-get_board_sys_clk(ulong dummy)
-{
-	u8 i, go_bit, rd_clks;
-	ulong val = 0;
-	u8 *pixis_base = (u8 *)PIXIS_BASE;
-
-	go_bit = in_8(pixis_base + PIXIS_VCTL);
-	go_bit &= 0x01;
-
-	rd_clks = in_8(pixis_base + PIXIS_VCFGEN0);
-	rd_clks &= 0x1C;
-
-	/*
-	 * Only if both go bit and the SCLK bit in VCFGEN0 are set
-	 * should we be using the AUX register. Remember, we also set the
-	 * GO bit to boot from the alternate bank on the on-board flash
-	 */
-
-	if (go_bit) {
-		if (rd_clks == 0x1c)
-			i = in_8(pixis_base + PIXIS_AUX);
-		else
-			i = in_8(pixis_base + PIXIS_SPD);
-	} else {
-		i = in_8(pixis_base + PIXIS_SPD);
-	}
-
-	i &= 0x07;
-
-	switch (i) {
-	case 0:
-		val = 33333333;
-		break;
-	case 1:
-		val = 40000000;
-		break;
-	case 2:
-		val = 50000000;
-		break;
-	case 3:
-		val = 66666666;
-		break;
-	case 4:
-		val = 83000000;
-		break;
-	case 5:
-		val = 100000000;
-		break;
-	case 6:
-		val = 133333333;
-		break;
-	case 7:
-		val = 166666666;
-		break;
-	}
-
-	return val;
-}
-
-
-#define MIIM_CIS8204_SLED_CON		0x1b
-#define MIIM_CIS8204_SLEDCON_INIT	0x1115
-/*
- * Hack to write all 4 PHYs with the LED values
- */
-int board_phy_config(struct phy_device *phydev)
-{
-	static int do_once;
-	uint phyid;
-	struct mii_dev *bus = phydev->bus;
-
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-	if (do_once)
-		return 0;
-
-	for (phyid = 0; phyid < 4; phyid++)
-		bus->write(bus, phyid, MDIO_DEVAD_NONE, MIIM_CIS8204_SLED_CON,
-				MIIM_CIS8204_SLEDCON_INIT);
-
-	do_once = 1;
-
-	return 0;
-}
-
-
-int board_eth_init(struct bd_info *bis)
-{
-#ifdef CONFIG_TSEC_ENET
-	struct fsl_pq_mdio_info mdio_info;
-	struct tsec_info_struct tsec_info[2];
-	int num = 0;
-
-#ifdef CONFIG_TSEC1
-	SET_STD_TSEC_INFO(tsec_info[num], 1);
-	if (is_serdes_configured(SGMII_TSEC1)) {
-		puts("eTSEC1 is in sgmii mode.\n");
-		tsec_info[num].flags |= TSEC_SGMII;
-	}
-	num++;
-#endif
-#ifdef CONFIG_TSEC3
-	SET_STD_TSEC_INFO(tsec_info[num], 3);
-	if (is_serdes_configured(SGMII_TSEC3)) {
-		puts("eTSEC3 is in sgmii mode.\n");
-		tsec_info[num].flags |= TSEC_SGMII;
-	}
-	num++;
-#endif
-
-	if (!num) {
-		printf("No TSECs initialized\n");
-
-		return 0;
-	}
-
-	if (is_serdes_configured(SGMII_TSEC1) ||
-	    is_serdes_configured(SGMII_TSEC3)) {
-		fsl_sgmii_riser_init(tsec_info, num);
-	}
-
-	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
-	mdio_info.name = DEFAULT_MII_NAME;
-	fsl_pq_mdio_init(bis, &mdio_info);
-
-	tsec_eth_init(bis, tsec_info, num);
-#endif
-	return pci_eth_init(bis);
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, struct bd_info *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	FT_FSL_PCI_SETUP;
-
-#ifdef CONFIG_FSL_SGMII_RISER
-	fsl_sgmii_riser_fdt_fixup(blob);
-#endif
-
-	return 0;
-}
-#endif
diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c
deleted file mode 100644
index 7bd462934aa5..000000000000
--- a/board/freescale/mpc8544ds/tlb.c
+++ /dev/null
@@ -1,74 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
-		      0, 0, BOOKE_PAGESZ_4K, 0),
-	/*
-	 * TLB 0:	64M	Non-cacheable, guarded
-	 * 0xfc000000	64M	Covers FLASH at 0xFE800000 and 0xFF800000
-	 * Out of reset this entry is only 4K.
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 0, BOOKE_PAGESZ_64M, 1),
-	/*
-	 * TLB 1:	1G	Non-cacheable, guarded
-	 * 0x80000000	1G	PCIE  8,9,a,b
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 1, BOOKE_PAGESZ_1G, 1),
-
-	/*
-	 * TLB 2:	256M	Non-cacheable, guarded
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 3:	256M	Non-cacheable, guarded
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 3, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 4:	64M	Non-cacheable, guarded
-	 * 0xe000_0000	1M	CCSRBAR
-	 * 0xe100_0000	255M	PCI IO range
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 4, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLB 5:	64M	Non-cacheable, guarded
-	 * 0xf8000000	64M	PIXIS 0xF8000000 - 0xFBFFFFFF
-	 */
-	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
-		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
-		      0, 5, BOOKE_PAGESZ_64M, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/configs/MPC8544DS_defconfig b/configs/MPC8544DS_defconfig
deleted file mode 100644
index 82f14d812262..000000000000
--- a/configs/MPC8544DS_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-CONFIG_PPC=y
-CONFIG_SYS_TEXT_BASE=0xFFF80000
-CONFIG_ENV_SIZE=0x2000
-CONFIG_ENV_SECT_SIZE=0x10000
-CONFIG_MPC85xx=y
-# CONFIG_CMD_ERRATA is not set
-CONFIG_TARGET_MPC8544DS=y
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_OF_STDOUT_VIA_ALIAS=y
-CONFIG_BOOTDELAY=10
-# CONFIG_CONSOLE_MUX is not set
-# CONFIG_MISC_INIT_R is not set
-CONFIG_HUSH_PARSER=y
-CONFIG_CMD_REGINFO=y
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_PCI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_HASH is not set
-CONFIG_CMD_EXT2=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xFFF70000
-CONFIG_SCSI_AHCI=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_PHY_ATHEROS=y
-CONFIG_PHY_BROADCOM=y
-CONFIG_PHY_DAVICOM=y
-CONFIG_PHY_LXT=y
-CONFIG_PHY_MARVELL=y
-CONFIG_PHY_NATSEMI=y
-CONFIG_PHY_REALTEK=y
-CONFIG_PHY_SMSC=y
-CONFIG_PHY_VITESSE=y
-CONFIG_PHY_GIGE=y
-CONFIG_E1000=y
-CONFIG_MII=y
-CONFIG_RTL8139=y
-CONFIG_TSEC_ENET=y
-CONFIG_SCSI=y
-CONFIG_SYS_NS16550=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_PCI=y
-CONFIG_USB_STORAGE=y
-CONFIG_VIDEO=y
-CONFIG_OF_LIBFDT=y
diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h
deleted file mode 100644
index f4f41da4988b..000000000000
--- a/include/configs/MPC8544DS.h
+++ /dev/null
@@ -1,408 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
- */
-
-/*
- * mpc8544ds board configuration file
- *
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_PCI1		1	/* PCI controller 1 */
-#define CONFIG_PCIE1		1	/* PCIE controller 1 (slot 1) */
-#define CONFIG_PCIE2		1	/* PCIE controller 2 (slot 2) */
-#define CONFIG_PCIE3		1	/* PCIE controller 3 (ULI bridge) */
-#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE 1	/* indirect PCI bridge support */
-#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
-
-#define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
-
-#ifndef __ASSEMBLY__
-#include <linux/stringify.h>
-extern unsigned long get_board_sys_clk(unsigned long dummy);
-#endif
-#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk(0) /* sysclk for MPC85xx */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE			/* toggle L2 cache */
-#define CONFIG_BTB			/* toggle branch predition */
-
-/*
- * Only possible on E500 Version 2 or newer cores.
- */
-#define CONFIG_ENABLE_36BIT_PHYS	1
-
-#define CONFIG_SYS_CCSRBAR		0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
-
-/* DDR Setup */
-#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	2
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS	0x51		/* DDR DIMM */
-
-/* Make sure required options are set */
-#ifndef CONFIG_SPD_EEPROM
-#error ("CONFIG_SPD_EEPROM is required")
-#endif
-
-/*
- * Memory map
- *
- * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
- *
- * 0x8000_0000	0xbfff_ffff	PCI Express Mem		1G non-cacheable
- *
- * 0xc000_0000	0xdfff_ffff	PCI			512M non-cacheable
- *
- * 0xe000_0000	0xe00f_ffff	CCSR			1M non-cacheable
- * 0xe100_0000	0xe3ff_ffff	PCI IO range		4M non-cacheable
- *
- * Localbus cacheable
- *
- * 0xf000_0000	0xf3ff_ffff	SDRAM			64M Cacheable
- * 0xf401_0000	0xf401_3fff	L1 for stack		4K Cacheable TLB0
- *
- * Localbus non-cacheable
- *
- * 0xf800_0000	0xf80f_ffff	NVRAM/CADMUS (*)	1M non-cacheable
- * 0xff00_0000	0xff7f_ffff	FLASH (2nd bank)	8M non-cacheable
- * 0xff80_0000	0xffff_ffff	FLASH (boot bank)	8M non-cacheable
- *
- */
-
-/*
- * Local Bus Definitions
- */
-#define CONFIG_SYS_BOOT_BLOCK		0xfc000000	/* boot TLB */
-
-#define CONFIG_SYS_FLASH_BASE		0xff800000	/* start of FLASH 8M */
-
-#define CONFIG_SYS_BR0_PRELIM		0xff801001
-#define CONFIG_SYS_BR1_PRELIM		0xfe801001
-
-#define CONFIG_SYS_OR0_PRELIM		0xff806e65
-#define CONFIG_SYS_OR1_PRELIM		0xff806e65
-
-#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE}
-
-#define CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000		/* Flash Erase Timeout (ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500		/* Flash Write Timeout (ms) */
-#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-
-#define CONFIG_SYS_LBC_NONCACHE_BASE	0xf8000000
-
-#define CONFIG_SYS_BR2_PRELIM		0xf8201001	/* port size 16bit */
-#define CONFIG_SYS_OR2_PRELIM		0xfff06ff7	/* 1MB Compact Flash area*/
-
-#define CONFIG_SYS_BR3_PRELIM		0xf8100801	/* port size 8bit */
-#define CONFIG_SYS_OR3_PRELIM		0xfff06ff7	/* 1MB PIXIS area*/
-
-#define CONFIG_FSL_PIXIS	1	/* use common PIXIS code */
-#define PIXIS_BASE	0xf8100000	/* PIXIS registers */
-#define PIXIS_ID		0x0	/* Board ID at offset 0 */
-#define PIXIS_VER		0x1	/* Board version at offset 1 */
-#define PIXIS_PVER		0x2	/* PIXIS FPGA version at offset 2 */
-#define PIXIS_RST		0x4	/* PIXIS Reset Control register */
-#define PIXIS_AUX		0x6	/* PIXIS Auxiliary register; Scratch
-					 * register */
-#define PIXIS_SPD		0x7	/* Register for SYSCLK speed */
-#define PIXIS_VCTL		0x10	/* VELA Control Register */
-#define PIXIS_VCFGEN0		0x12	/* VELA Config Enable 0 */
-#define PIXIS_VCFGEN1		0x13	/* VELA Config Enable 1 */
-#define PIXIS_VBOOT		0x16	/* VELA VBOOT Register */
-#define PIXIS_VBOOT_FMAP	0x80	/* VBOOT - CFG_FLASHMAP */
-#define PIXIS_VBOOT_FBANK	0x40	/* VBOOT - CFG_FLASHBANK */
-#define PIXIS_VSPEED0		0x17	/* VELA VSpeed 0 */
-#define PIXIS_VSPEED1		0x18	/* VELA VSpeed 1 */
-#define PIXIS_VCLKH		0x19	/* VELA VCLKH register */
-#define PIXIS_VCLKL		0x1A	/* VELA VCLKL register */
-#define PIXIS_VSPEED2		0x1d	/* VELA VSpeed 2 */
-#define CONFIG_SYS_PIXIS_VBOOT_MASK	0x40    /* Reset altbank mask*/
-#define PIXIS_VSPEED2_TSEC1SER	0x2
-#define PIXIS_VSPEED2_TSEC3SER	0x1
-#define PIXIS_VCFGEN1_TSEC1SER	0x20
-#define PIXIS_VCFGEN1_TSEC3SER	0x40
-#define PIXIS_VSPEED2_MASK	(PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
-#define PIXIS_VCFGEN1_MASK	(PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
-
-#define CONFIG_SYS_INIT_RAM_LOCK      1
-#define CONFIG_SYS_INIT_RAM_ADDR      0xf4010000      /* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_SIZE       0x00004000      /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)	/* Reserved for malloc */
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED	400000
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x3100
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-#define CONFIG_SYS_PCIE_VIRT		0x80000000	/* 1G PCIE TLB */
-#define CONFIG_SYS_PCIE_PHYS		0x80000000	/* 1G PCIE TLB */
-#define CONFIG_SYS_PCI_VIRT		0xc0000000	/* 512M PCI TLB */
-#define CONFIG_SYS_PCI_PHYS		0xc0000000	/* 512M PCI TLB */
-
-#define CONFIG_SYS_PCI1_MEM_VIRT	0xc0000000
-#define CONFIG_SYS_PCI1_MEM_BUS	0xc0000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	0xc0000000
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCI1_IO_VIRT	0xe1000000
-#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS	0xe1000000
-#define CONFIG_SYS_PCI1_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 2, Slot 1, tgtid 1, Base address 9000 */
-#define CONFIG_SYS_PCIE2_NAME		"Slot 1"
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE2_MEM_BUS	0x80000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0x80000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xe1010000
-#define CONFIG_SYS_PCIE2_IO_BUS	0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xe1010000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 1, Slot 2,tgtid 2, Base address a000 */
-#define CONFIG_SYS_PCIE1_NAME		"Slot 2"
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xe1020000
-#define CONFIG_SYS_PCIE1_IO_BUS	0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xe1020000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 3, direct to uli, tgtid 3, Base address b000 */
-#define CONFIG_SYS_PCIE3_NAME		"ULI"
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xb0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x00100000	/* 1M */
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xb0100000	/* reuse mem LAW */
-#define CONFIG_SYS_PCIE3_IO_BUS	0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xb0100000	/* reuse mem LAW */
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00100000	/* 1M */
-#define CONFIG_SYS_PCIE3_MEM_VIRT2	0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_BUS2	0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_PHYS2	0xb0200000
-#define CONFIG_SYS_PCIE3_MEM_SIZE2	0x00200000	/* 1M */
-
-#if defined(CONFIG_PCI)
-
-/*PCIE video card used*/
-#define VIDEO_IO_OFFSET		CONFIG_SYS_PCIE2_IO_VIRT
-
-/*PCI video card used*/
-/*#define VIDEO_IO_OFFSET	CONFIG_SYS_PCI1_IO_VIRT*/
-
-/* video */
-
-#if defined(CONFIG_VIDEO)
-#define CONFIG_BIOSEMU
-#define CONFIG_ATI_RADEON_FB
-#define CONFIG_VIDEO_LOGO
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
-#endif
-
-
-#ifndef CONFIG_PCI_PNP
-	#define PCI_ENET0_IOADDR	CONFIG_SYS_PCI1_IO_BUS
-	#define PCI_ENET0_MEMADDR	CONFIG_SYS_PCI1_IO_BUS
-	#define PCI_IDSEL_NUMBER	0x11	/* IDSEL = AD11 */
-#endif
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
-#ifdef CONFIG_SCSI_AHCI
-#define CONFIG_SATA_ULI5288
-#define CONFIG_SYS_SCSI_MAX_SCSI_ID	4
-#define CONFIG_SYS_SCSI_MAX_LUN	1
-#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
-#endif /* CONFIG_SCSI_AHCI */
-
-#endif	/* CONFIG_PCI */
-
-#if defined(CONFIG_TSEC_ENET)
-
-#define CONFIG_MII_DEFAULT_TSEC	1	/* Allow unregistered phys */
-#define CONFIG_TSEC1	1
-#define CONFIG_TSEC1_NAME	"eTSEC1"
-#define CONFIG_TSEC3	1
-#define CONFIG_TSEC3_NAME	"eTSEC3"
-
-#define CONFIG_PIXIS_SGMII_CMD
-#define CONFIG_FSL_SGMII_RISER	1
-#define SGMII_RISER_PHY_OFFSET	0x1c
-
-#define TSEC1_PHY_ADDR		0
-#define TSEC3_PHY_ADDR		1
-
-#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-
-#define TSEC1_PHYIDX		0
-#define TSEC3_PHYIDX		0
-
-#define CONFIG_ETHPRIME		"eTSEC1"
-#endif	/* CONFIG_TSEC_ENET */
-
-/*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * USB
- */
-
-#ifdef CONFIG_USB_EHCI_HCD
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_PCI_EHCI_DEVICE			0
-#endif
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-
-/* The mac addresses for all ethernet interface */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_IPADDR	192.168.1.251
-
-#define CONFIG_HOSTNAME	"8544ds_unknown"
-#define CONFIG_ROOTPATH	"/nfs/mpc85xx"
-#define CONFIG_BOOTFILE	"8544ds/uImage.uboot"
-#define CONFIG_UBOOTPATH	8544ds/u-boot.bin	/* TFTP server */
-
-#define CONFIG_SERVERIP	192.168.1.1
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK	255.255.0.0
-
-#define CONFIG_LOADADDR	1000000	/*default location for tftp and bootm*/
-
-#define	CONFIG_EXTRA_ENV_SETTINGS				\
-"netdev=eth0\0"						\
-"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"			\
-"tftpflash=tftpboot $loadaddr $uboot; "			\
-	"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" +$filesize; "	\
-	"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
-		" +$filesize; "	\
-	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" $filesize; "	\
-	"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
-		" +$filesize; "	\
-	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
-		" $filesize\0"	\
-"consoledev=ttyS0\0"				\
-"ramdiskaddr=2000000\0"			\
-"ramdiskfile=8544ds/ramdisk.uboot\0"		\
-"fdtaddr=1e00000\0"				\
-"fdtfile=8544ds/mpc8544ds.dtb\0"		\
-"bdev=sda3\0"
-
-#define CONFIG_NFSBOOTCOMMAND		\
- "setenv bootargs root=/dev/nfs rw "	\
- "nfsroot=$serverip:$rootpath "		\
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;"	\
- "tftp $loadaddr $bootfile;"		\
- "tftp $fdtaddr $fdtfile;"		\
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND		\
- "setenv bootargs root=/dev/ram rw "	\
- "console=$consoledev,$baudrate $othbootargs;"	\
- "tftp $ramdiskaddr $ramdiskfile;"	\
- "tftp $loadaddr $bootfile;"		\
- "tftp $fdtaddr $fdtfile;"		\
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND		\
- "setenv bootargs root=/dev/$bdev rw "	\
- "console=$consoledev,$baudrate $othbootargs;"	\
- "tftp $loadaddr $bootfile;"		\
- "tftp $fdtaddr $fdtfile;"		\
- "bootm $loadaddr - $fdtaddr"
-
-#endif	/* __CONFIG_H */
-- 
2.17.1