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From: Qingqing Zhuo <qingqing.zhuo@amd.com>
To: amd-gfx@lists.freedesktop.org
Cc: Wesley Chalmers <Wesley.Chalmers@amd.com>,
	Eryk.Brol@amd.com, Sunpeng.Li@amd.com, Harry.Wentland@amd.com,
	qingqing.zhuo@amd.com, Rodrigo.Siqueira@amd.com,
	roman.li@amd.com, Anson.Jacob@amd.com, Aurabindo.Pillai@amd.com,
	Bhawanpreet.Lakha@amd.com, bindu.r@amd.com
Subject: [PATCH 04/14] drm/amd/display: Unblank hubp based on plane enable
Date: Thu, 11 Feb 2021 16:44:34 -0500	[thread overview]
Message-ID: <20210211214444.8348-5-qingqing.zhuo@amd.com> (raw)
In-Reply-To: <20210211214444.8348-1-qingqing.zhuo@amd.com>

From: Wesley Chalmers <Wesley.Chalmers@amd.com>

[Why]
We are not implementing the planned new HW sequence
to disable HUBP.

[How]
Revert most related changes to minimize possibility
of regression.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com>
---
 .../gpu/drm/amd/display/dc/basics/dc_common.c | 20 ++++++-------------
 .../gpu/drm/amd/display/dc/basics/dc_common.h |  4 ++--
 .../drm/amd/display/dc/dcn20/dcn20_hwseq.c    |  2 +-
 3 files changed, 9 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/basics/dc_common.c b/drivers/gpu/drm/amd/display/dc/basics/dc_common.c
index ad04ef98e652..b2fc4f8e6482 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/dc_common.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/dc_common.c
@@ -49,24 +49,20 @@ bool is_rgb_cspace(enum dc_color_space output_color_space)
 	}
 }
 
-bool is_child_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
+bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
 {
 	if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
 		return true;
-	if (pipe_ctx->bottom_pipe && is_child_pipe_tree_visible(pipe_ctx->bottom_pipe))
-		return true;
-	if (pipe_ctx->next_odm_pipe && is_child_pipe_tree_visible(pipe_ctx->next_odm_pipe))
+	if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
 		return true;
 	return false;
 }
 
-bool is_parent_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
+bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
 {
 	if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
 		return true;
-	if (pipe_ctx->top_pipe && is_parent_pipe_tree_visible(pipe_ctx->top_pipe))
-		return true;
-	if (pipe_ctx->prev_odm_pipe && is_parent_pipe_tree_visible(pipe_ctx->prev_odm_pipe))
+	if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
 		return true;
 	return false;
 }
@@ -75,13 +71,9 @@ bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
 {
 	if (pipe_ctx->plane_state && pipe_ctx->plane_state->visible)
 		return true;
-	if (pipe_ctx->top_pipe && is_parent_pipe_tree_visible(pipe_ctx->top_pipe))
-		return true;
-	if (pipe_ctx->bottom_pipe && is_child_pipe_tree_visible(pipe_ctx->bottom_pipe))
-		return true;
-	if (pipe_ctx->prev_odm_pipe && is_parent_pipe_tree_visible(pipe_ctx->prev_odm_pipe))
+	if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
 		return true;
-	if (pipe_ctx->next_odm_pipe && is_child_pipe_tree_visible(pipe_ctx->next_odm_pipe))
+	if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
 		return true;
 	return false;
 }
diff --git a/drivers/gpu/drm/amd/display/dc/basics/dc_common.h b/drivers/gpu/drm/amd/display/dc/basics/dc_common.h
index b061497480b8..7c0cbf47e8ce 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/dc_common.h
+++ b/drivers/gpu/drm/amd/display/dc/basics/dc_common.h
@@ -30,9 +30,9 @@
 
 bool is_rgb_cspace(enum dc_color_space output_color_space);
 
-bool is_child_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
+bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
 
-bool is_parent_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
+bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
 
 bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index 0726fb435e2a..b79a17f6a9cc 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1575,7 +1575,7 @@ static void dcn20_update_dchubp_dpp(
 
 
 
-	if (is_pipe_tree_visible(pipe_ctx))
+	if (pipe_ctx->update_flags.bits.enable)
 		dc->hwss.set_hubp_blank(dc, pipe_ctx, false);
 }
 
-- 
2.17.1

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  parent reply	other threads:[~2021-02-11 21:45 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-11 21:44 [PATCH 00/14] DC Patches Feb 15th, 2021 Qingqing Zhuo
2021-02-11 21:44 ` [PATCH 01/14] drm/amd/display: Change ABM sample rate Qingqing Zhuo
2021-02-11 21:44 ` [PATCH 02/14] drm/amd/display: remove global optimize seamless boot stream count Qingqing Zhuo
2021-02-11 21:44 ` [PATCH 03/14] drm/amd/display: Old path for enabling DPG Qingqing Zhuo
2021-02-11 21:44 ` Qingqing Zhuo [this message]
2021-02-11 21:44 ` [PATCH 05/14] drm/amd/display: changing sr exit latency Qingqing Zhuo
2021-02-11 21:44 ` [PATCH 06/14] drm/amd/display: Add dc_dmub_srv helpers for in/out DMCUB commands Qingqing Zhuo
2021-02-11 21:44 ` [PATCH 07/14] drm/amd/display: Fix MPC OGAM power on/off sequence Qingqing Zhuo
2021-02-11 21:44 ` [PATCH 08/14] drm/amd/display: Populate dcn2.1 bounding box before state duplication Qingqing Zhuo
2021-02-11 21:44 ` [PATCH 09/14] drm/amd/display: Add Freesync HDMI support to DM Qingqing Zhuo
2021-02-18 22:31   ` Nathan Chancellor
2021-02-11 21:44 ` [PATCH 10/14] drm/amd/display: Copy over soc values before bounding box creation Qingqing Zhuo
2021-02-11 21:44 ` [PATCH 11/14] drm/amd/display: AVMUTE simplification Qingqing Zhuo
2021-02-11 21:44 ` [PATCH 12/14] drm/amd/display: Implement transmitter control v1.7 Qingqing Zhuo
2021-02-11 21:44 ` [PATCH 13/14] drm/amd/display: [FW Promotion] Release 0.0.52 Qingqing Zhuo
2021-02-11 21:44 ` [PATCH 14/14] drm/amd/display: 3.2.123 Qingqing Zhuo
2021-02-16 16:01 ` [PATCH 00/14] DC Patches Feb 15th, 2021 Wheeler, Daniel

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